Digital PLLs: The modern timing reference for radar and communication systems

Digital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS. This paper will briefly trace the path from the (re-)discover of this approach to the more recent solutions, discussing the main characteristics of key building blocks and their limitations, both the ones that can be removed by digital calibrations, such as the non-linearities, and the most fundamental one, the noise, that still calls for a sound knowledge of analog design techniques. Recent results are also presented and perspectives discussed.