BERTULESSI, LUCA
BERTULESSI, LUCA
DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS
2019-01-01 Grimaldi, Luigi; Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
2021-01-01 Santiccioli, A.; Mercandelli, M.; Dartizio, S. M.; Tesolin, F.; Karman, S.; Shehata, A.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
2023-01-01 Dartizio, Simone M.; Tesolin, Francesco; Castoro, Giacomo; Buccoleri, Francesco; Lanzoni, Luca; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
2023-01-01 Castoro, Giacomo; Dartizio, Simone M.; Tesolin, Francesco; Buccoleri, Francesco; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters
2022-01-01 Scaletti, Lorenzo; Be', Gabriele; Parisi, Angelo; Bertulessi, Luca; Ricci, Luca; Mercandelli, Mario; Levantino, Salvatore; Samori, Carlo; Bonfanti, ANDREA GIOVANNI
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
2022-01-01 Mercandelli, Mario; Santiccioli, Alessio; Parisi, Angelo; Bertulessi, Luca; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
2020-01-01 Mercandelli, M.; Santiccioli, A.; Parisi, A.; Bertulessi, L.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S.
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
2022-01-01 Dartizio, Simone M.; Tesolin, Francesco; Mercandelli, Mario; Santiccioli, Alessio; Shehata, Abanob; Karman, Saleh; Bertulessi, Luca; Buccoleri, Francesco; Avallone, Luca; Parisi, Angelo; Lacaita, Andrea L.; Kennedy, Michael P.; Samori, Carlo; Levantino, Salvatore
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
2021-01-01 Mercandelli, M.; Santiccioli, A.; Dartizio, S. M.; Shehata, A.; Tesolin, F.; Karman, S.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation
2018-01-01 Cherniak, Dmytro; Grimaldi, Luigi; Bertulessi, Luca; Nonis, Roberto; Samori, Carlo; Levantino, Salvatore
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
2018-01-01 Cherniak, Dmytro; Grimaldi, Luigi; Bertulessi, Luca; Samori, Carlo; Nonis, Roberto; Levantino, Salvatore
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL
2020-01-01 Cherniak, Dmytro; Mercandelli, Mario; Bertulessi, Luca; Padovan, Fabio; Grimaldi, Luigi; Santiccioli, Alessio; Aichner, Michael; Samori, Carlo; Levantino, Salvatore
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS
2023-01-01 Ricci, L.; Scaletti, L.; Be', G.; Rocco, M.; Bertulessi, L.; Levantino, S.; Lacaita, A.; Samori, C.; Bonfanti, A.
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
2021-01-01 Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
2019-01-01 Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking
2020-01-01 Santiccioli, Alessio; Mercandelli, Mario; Bertulessi, Luca; Parisi, Angelo; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
2020-01-01 Santiccioli, A.; Mercandelli, M.; Bertulessi, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S.
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
2022-01-01 Dartizio, S. M.; Buccoleri, F.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Iesurum, A.; Steffan, G.; Cherniak, D.; Bertulessi, L.; Bevilacqua, A.; Samori, C.; Lacaita, A. L.; Levantino, S.
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023-01-01 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
2022-01-01 Be', G.; Parisi, A.; Bertulessi, L.; Ricci, L.; Scaletti, L.; Mercandelli, M.; Lacaita, A. L.; Levantino, S.; Samori, C.; Bonfanti, A.