PARISI, ANGELO

PARISI, ANGELO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 11 di 11 (tempo di esecuzione: 0.008 secondi).
Titolo Data di pubblicazione Autori File
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 1-gen-2022 Lorenzo ScalettiGabriele BeAngelo ParisiLuca BertulessiLuca RicciMario MercandelliSalvatore LevantinoCarlo SamoriAndrea Bonfanti
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2021 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 1-gen-2020 Mercandelli M.Santiccioli A.Parisi A.Bertulessi L.Lacaita A. L.Samori C.Levantino S. +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2021 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Santiccioli A.Mercandelli M.Bertulessi L.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 1-gen-2021 Angelo ParisiMario MercandelliCarlo SamoriAndrea Leonardo Lacaita
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 1-gen-2021 Parisi, A.Tesolin, F.Mercandelli, M.Bertulessi, L.Lacaita, A. L.
Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits 1-gen-2021 L. ScalettiA. ParisiL. Bertulessi