An LO phase-shifting system based on digi- tal fractional-N bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to- time converter (DTC) nonlinearities. Synchronization between fractional-N PLL cores is achieved by clocking with the same reference clock the 16 modulator driving the frequency divider of each core. The adoption of a digital phase-offset correction technique canceling out timing skews greatly simplifies the reference-clock distribution and DTC matching. A dual-core prototype is implemented in a standard 28-nm CMOS process, where each element occupies 0.23-mm2 area and dissipates 20-mW power. An arbitrary phase shift between the LO outputs can be set over the 360◦ range with a resolution of 0.7 millidegree (19 bits). The rms phase accuracy is 0.76°, and the peak-to- peak phase error is 2.1°, without requiring any linearity or gain calibration. Each LO element features a −58.7 dBc in-band fractional spur and a −70 dBc reference spur, with a jitter versus power figure-of-merit of −253.5 and −250.0 dB for integer-N and fractional-N channels, respectively. The combined outputs of the two PLL cores reach an absolute jitter integrated from 1 kHz to 100 MHz (including spurs) of 38.2 and 59.78 fs, in integer-N and near-integer fractional-N operations, respectively.

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays

Tesolin, Francesco;Dartizio, Simone M.;Buccoleri, Francesco;Santiccioli, Alessio;Bertulessi, Luca;Samori, Carlo;Lacaita, Andrea L.;Levantino, Salvatore
2023-01-01

Abstract

An LO phase-shifting system based on digi- tal fractional-N bang-bang phase-locked loops (PLLs) in the 8.5–10.0-GHz range is presented. A direct phase modulation method is leveraged to perform LO phase-shifting directly within the frequency synthesizer, leading to an inherently linear phase-shifting characteristic, even in the presence of digital-to- time converter (DTC) nonlinearities. Synchronization between fractional-N PLL cores is achieved by clocking with the same reference clock the 16 modulator driving the frequency divider of each core. The adoption of a digital phase-offset correction technique canceling out timing skews greatly simplifies the reference-clock distribution and DTC matching. A dual-core prototype is implemented in a standard 28-nm CMOS process, where each element occupies 0.23-mm2 area and dissipates 20-mW power. An arbitrary phase shift between the LO outputs can be set over the 360◦ range with a resolution of 0.7 millidegree (19 bits). The rms phase accuracy is 0.76°, and the peak-to- peak phase error is 2.1°, without requiring any linearity or gain calibration. Each LO element features a −58.7 dBc in-band fractional spur and a −70 dBc reference spur, with a jitter versus power figure-of-merit of −253.5 and −250.0 dB for integer-N and fractional-N channels, respectively. The combined outputs of the two PLL cores reach an absolute jitter integrated from 1 kHz to 100 MHz (including spurs) of 38.2 and 59.78 fs, in integer-N and near-integer fractional-N operations, respectively.
2023
CMOS
PLL
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1245917
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