RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

BERTULESSI, LUCA
 Distribuzione geografica
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Continente #
NA - Nord America 1.695
EU - Europa 1.390
AS - Asia 558
SA - Sud America 148
AF - Africa 19
Continente sconosciuto - Info sul continente non disponibili 3
OC - Oceania 3
Totale 3.816
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Nazione #
US - Stati Uniti d'America 1.655
IT - Italia 762
SG - Singapore 259
BR - Brasile 133
AT - Austria 112
NL - Olanda 80
CN - Cina 76
DE - Germania 74
IE - Irlanda 61
FR - Francia 51
VN - Vietnam 51
ES - Italia 50
FI - Finlandia 47
GB - Regno Unito 35
IN - India 34
CA - Canada 28
KR - Corea 27
JP - Giappone 21
BE - Belgio 20
SE - Svezia 20
UA - Ucraina 19
JO - Giordania 16
HK - Hong Kong 15
TW - Taiwan 13
RU - Federazione Russa 10
MX - Messico 9
PL - Polonia 9
TR - Turchia 9
AR - Argentina 8
BD - Bangladesh 8
CH - Svizzera 8
BJ - Benin 6
CI - Costa d'Avorio 5
GR - Grecia 4
ID - Indonesia 4
IL - Israele 4
RO - Romania 4
AL - Albania 3
AZ - Azerbaigian 3
CZ - Repubblica Ceca 3
EE - Estonia 3
EU - Europa 3
IQ - Iraq 3
PH - Filippine 3
ZA - Sudafrica 3
AU - Australia 2
KZ - Kazakistan 2
LA - Repubblica Popolare Democratica del Laos 2
LV - Lettonia 2
MA - Marocco 2
NO - Norvegia 2
PT - Portogallo 2
VE - Venezuela 2
AM - Armenia 1
BG - Bulgaria 1
BO - Bolivia 1
CL - Cile 1
CR - Costa Rica 1
DK - Danimarca 1
EC - Ecuador 1
EG - Egitto 1
GA - Gabon 1
HN - Honduras 1
HU - Ungheria 1
IR - Iran 1
IS - Islanda 1
KG - Kirghizistan 1
LK - Sri Lanka 1
LT - Lituania 1
LU - Lussemburgo 1
MK - Macedonia 1
NP - Nepal 1
NZ - Nuova Zelanda 1
PA - Panama 1
PE - Perù 1
PK - Pakistan 1
RS - Serbia 1
SA - Arabia Saudita 1
SC - Seychelles 1
SK - Slovacchia (Repubblica Slovacca) 1
SY - Repubblica araba siriana 1
UY - Uruguay 1
Totale 3.816
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Città #
Milan 321
Chandler 248
Singapore 158
Santa Clara 147
Fairfield 140
Ashburn 108
Vienna 99
Seattle 76
Woodbridge 76
Houston 68
Wilmington 63
Cambridge 52
Dublin 48
Málaga 47
Ann Arbor 44
Boardman 40
Council Bluffs 37
Amsterdam 35
Redmond 30
Lawrence 24
Legnano 24
Turin 24
Beijing 23
Munich 23
Castilenti 22
Los Angeles 22
Palazzolo sull'Oglio 22
Brescia 21
Helsinki 21
New York 21
San Diego 21
Dong Ket 20
Medford 20
Frankfurt am Main 17
Seoul 17
Amman 16
Ottawa 14
Shanghai 14
Brussels 13
London 13
Bengaluru 12
Redwood City 12
Rome 12
Sesto San Giovanni 12
Tokyo 12
Turku 12
Lappeenranta 10
Dearborn 9
Monza 9
Pasadena 9
São Paulo 8
Columbus 7
Roubaix 7
Cotonou 6
Hanoi 6
Irvine 6
San Jose 6
Washington 6
Zurich 6
Abidjan 5
Central District 5
Chicago 5
Edinburgh 5
Genoa 5
Gessate 5
Goodyear 5
Grafing 5
Lainate 5
Lecco 5
Naples 5
Nuremberg 5
Princeton 5
Stockholm 5
Vimodrone 5
Wroclaw 5
Bari 4
Boydton 4
Chengdu 4
Cortenuova 4
Duncan 4
Fara Gera D'adda 4
Jakarta 4
New Taipei 4
Norwood 4
Padova 4
San Francisco 4
San Mateo 4
Taipei 4
Anyang-si 3
Athens 3
Baku 3
Barge 3
Belo Horizonte 3
Berlin 3
Brasília 3
Carugate 3
Dallas 3
Eindhoven 3
Fremont 3
Graz 3
Totale 2.584
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Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 230
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 194
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 172
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 143
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 142
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 142
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 138
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 136
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 129
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 126
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 113
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 113
Analysis of power efficiency in high-performance class-B oscillators 109
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 107
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 107
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 104
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 102
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 98
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 98
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 93
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 86
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization 79
Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits 78
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 74
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 73
Concurrent effect of redundancy and switching algorithms in SAR ADCs 69
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 69
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 69
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 68
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 67
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 65
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process 63
A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process 61
Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications 60
Digital PLLs: The modern timing reference for radar and communication systems 57
A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter 55
Circuito integrato per l'estrazione di caratteristiche di segnale 49
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 48
A Digital PLL with Multi-tap LMS-based Bandwidth Control 44
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity 28
Hardware Accelerator for Feature Extraction from sensors’ physical signals 28
A Multi-Input Error-Feedback Architecture for Noise-Shaping SAR ADCs 21
LATCH COMPARATOR 17
NESTED FLOATING-INVERTER BASED AMPLIFIER 13
Totale 3.937
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Categoria #
all - tutte 15.678
article - articoli 6.799
book - libri 0
conference - conferenze 8.100
curatela - curatele 0
other - altro 0
patent - brevetti 403
selected - selezionate 0
volume - volumi 376
Totale 31.356
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/202025 0 0 0 0 0 0 0 0 0 0 0 25
2020/2021413 50 46 64 26 27 8 9 12 36 51 16 68
2021/2022468 12 20 43 59 27 10 28 30 71 16 110 42
2022/2023861 62 69 34 110 82 83 24 38 159 106 68 26
2023/2024428 27 59 43 25 32 45 38 26 38 27 22 46
2024/20251.362 10 65 86 24 201 69 108 117 223 100 237 122
Totale 3.937