RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

BERTULESSI, LUCA
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 3.784
EU - Europa 3.028
AS - Asia 2.272
SA - Sud America 349
Continente sconosciuto - Info sul continente non disponibili 141
AF - Africa 91
OC - Oceania 7
Totale 9.672
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 3.654
IT - Italia 1.166
RU - Federazione Russa 970
SG - Singapore 678
CN - Cina 565
BR - Brasile 280
HK - Hong Kong 202
VN - Vietnam 201
JP - Giappone 158
KR - Corea 154
FR - Francia 130
DE - Germania 121
AT - Austria 120
NL - Olanda 109
CA - Canada 75
IN - India 73
GB - Regno Unito 67
IE - Irlanda 66
ES - Italia 59
FI - Finlandia 54
BD - Bangladesh 50
TW - Taiwan 47
UA - Ucraina 29
AR - Argentina 28
MX - Messico 28
MA - Marocco 27
SE - Svezia 26
BE - Belgio 25
PL - Polonia 23
TR - Turchia 23
ZA - Sudafrica 18
JO - Giordania 17
ID - Indonesia 16
IQ - Iraq 14
EC - Ecuador 12
PH - Filippine 12
CH - Svizzera 11
EG - Egitto 11
PK - Pakistan 10
CI - Costa d'Avorio 9
CO - Colombia 8
PT - Portogallo 8
AZ - Azerbaigian 6
BJ - Benin 6
CR - Costa Rica 6
GR - Grecia 6
VE - Venezuela 6
IL - Israele 5
RO - Romania 5
SA - Arabia Saudita 5
UZ - Uzbekistan 5
AE - Emirati Arabi Uniti 4
AL - Albania 4
AU - Australia 4
CL - Cile 4
JM - Giamaica 4
OM - Oman 4
UY - Uruguay 4
BG - Bulgaria 3
CZ - Repubblica Ceca 3
DZ - Algeria 3
EE - Estonia 3
ET - Etiopia 3
EU - Europa 3
KE - Kenya 3
KZ - Kazakistan 3
NI - Nicaragua 3
NP - Nepal 3
PY - Paraguay 3
RS - Serbia 3
BA - Bosnia-Erzegovina 2
BZ - Belize 2
DO - Repubblica Dominicana 2
GA - Gabon 2
HU - Ungheria 2
KG - Kirghizistan 2
LA - Repubblica Popolare Democratica del Laos 2
LT - Lituania 2
LV - Lettonia 2
MY - Malesia 2
NO - Norvegia 2
NZ - Nuova Zelanda 2
PA - Panama 2
PE - Perù 2
SC - Seychelles 2
TH - Thailandia 2
TT - Trinidad e Tobago 2
AM - Armenia 1
AO - Angola 1
AW - Aruba 1
BB - Barbados 1
BH - Bahrain 1
BO - Bolivia 1
CV - Capo Verde 1
CY - Cipro 1
DK - Danimarca 1
DM - Dominica 1
GE - Georgia 1
GF - Guiana Francese 1
HN - Honduras 1
Totale 9.515
Salva come PNG Salva come JPEG
Città #
Ashburn 642
Milan 515
Singapore 429
San Jose 382
Chandler 248
Santa Clara 170
Hong Kong 165
Fairfield 141
Tokyo 128
Seoul 125
Moscow 123
Los Angeles 117
Hefei 115
Council Bluffs 106
Vienna 101
Beijing 100
Houston 84
Seattle 80
Woodbridge 78
The Dalles 75
Wilmington 65
New York 62
Kent 61
Dublin 53
Cambridge 52
Ho Chi Minh City 50
Rome 50
Málaga 48
Amsterdam 46
Ann Arbor 44
Boardman 43
Frankfurt am Main 42
Dallas 39
Lauterbourg 38
Shanghai 36
Turin 34
Hanoi 33
North Charleston 32
Redmond 30
São Paulo 30
Buffalo 26
Taipei 26
Helsinki 25
Orem 25
Chicago 24
Lawrence 24
Legnano 24
Brescia 23
Munich 23
Castilenti 22
London 22
Palazzolo sull'Oglio 22
San Diego 21
Dong Ket 20
Medford 20
Amman 17
Montreal 16
Monza 15
Ottawa 15
Bengaluru 13
Brussels 13
Chennai 13
Denver 13
Kenitra 13
Lappeenranta 13
Johannesburg 12
Redwood City 12
Sesto San Giovanni 12
Turku 12
Warsaw 12
Washington 12
Chengdu 11
Guangzhou 11
Stockholm 11
Toronto 11
Jakarta 10
Las Vegas 10
Naples 10
Pasadena 10
Roubaix 10
Austin 9
Brooklyn 9
Da Nang 9
Dearborn 9
Genoa 9
San Francisco 9
Abidjan 8
Ames 8
Bari 8
Casablanca 8
Columbus 8
Mexico City 8
Zurich 8
Ankara 7
Atlanta 7
Brasília 7
Changsha 7
Charlottesville 7
Irvine 7
Manchester 7
Totale 5.625
Salva come PNG Salva come JPEG
Nome #
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 380
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 310
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 299
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 271
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 263
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 259
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 258
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 255
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 252
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 251
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 245
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 241
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 232
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 231
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk 230
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 228
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 227
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization 224
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 218
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 216
A Multi-Input Error-Feedback Architecture for Noise-Shaping SAR ADCs 214
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 210
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 209
Concurrent effect of redundancy and switching algorithms in SAR ADCs 208
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 204
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 201
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 192
Power-Reduction Technique for Time-to-Digital Converters in 28-nm CMOS process 189
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 188
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 178
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 177
Analysis of power efficiency in high-performance class-B oscillators 169
LATCH COMPARATOR 166
Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits 162
NESTED FLOATING-INVERTER BASED AMPLIFIER 152
Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications 151
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 149
An Analysis of Switch Thermal Noise in SAR Converters 147
A 20MHz-BW 12.3-ENOB NS SAR ADC with a 3rd-order Multi-Input Filter and a PVT-Robust Ratio-Based FIA 145
A Novel Push-Pull Input Buffer for Wideband ADCs with Improved High-Frequency Linearity 141
Circuito integrato per l'estrazione di caratteristiche di segnale 138
A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process 136
A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter 131
A Digital PLL with Multi-tap LMS-based Bandwidth Control 130
Hardware Accelerator for Feature Extraction from sensors’ physical signals 124
A 20 MHz-BW 12.3-ENOB 3rd-Order Noise-Shaping SAR ADC with Multi-Input Architecture and PVT-Robust Ratio-Based FIA 116
Digital PLLs: The modern timing reference for radar and communication systems 104
Efficiency Comparison of FVF-Based LDO Voltage Regulators for Ultra-Fast Response Time 90
11.3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension 57
A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension 4
Totale 9.672
Salva come PNG Salva come JPEG
Categoria #
all - tutte 27.207
article - articoli 11.372
book - libri 0
conference - conferenze 13.737
curatela - curatele 0
other - altro 0
patent - brevetti 1.542
selected - selezionate 0
volume - volumi 556
Totale 54.414
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/2022456 0 20 43 59 27 10 28 30 71 16 110 42
2022/2023861 62 69 34 110 82 83 24 38 159 106 68 26
2023/2024428 27 59 43 25 32 45 38 26 38 27 22 46
2024/20251.452 10 65 86 24 201 69 108 117 223 100 237 212
2025/20265.279 887 776 256 535 371 253 851 208 328 355 206 253
2026/2027366 204 162 0 0 0 0 0 0 0 0 0 0
Totale 9.672