This paper presents a high-speed and low-noise comparator implemented in a 28-nm bulk CMOS technology with a 0.9-V supply voltage. The comparator is designed for a 12- bit 200-MSps successive-approximation-register (SAR) analogto- digital converter (ADC). Simulations show an input-referred noise of 163 muV and a reset-out delay of 110-ps for an input differential voltage of 100 muV. The energy per conversion is 595 fJ/conv and the Figure-of-Merit is 15.8 nJmuV(exp 2), better than the state of the art.

A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process

L. Ricci;L. Bertulessi;A. Bonfanti
2021-01-01

Abstract

This paper presents a high-speed and low-noise comparator implemented in a 28-nm bulk CMOS technology with a 0.9-V supply voltage. The comparator is designed for a 12- bit 200-MSps successive-approximation-register (SAR) analogto- digital converter (ADC). Simulations show an input-referred noise of 163 muV and a reset-out delay of 110-ps for an input differential voltage of 100 muV. The energy per conversion is 595 fJ/conv and the Figure-of-Merit is 15.8 nJmuV(exp 2), better than the state of the art.
2021
SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME
9783800755882
ADC, SAR, CMOS, Comparator,
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1186275
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