This paper reviews state-of-the-art skew correction methods in time-interleaved (TI) analog-to-digital converters (ADCs) and introduces a novel mixed-signal skew correction technique based on dithering the control word of a digital-totime converter (DTC), which significantly relaxes the stringent DTC resolution requirements. Simulation results of a 10 GS/s 8– bit 16-core TI-ADC reveal that the proposed technique reduces the required DTC resolution by a factor of 4x and improves the spurious-free dynamic range (SFDR) by up to 10 dB with a negligible noise penalty.

A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter

G. Be';M. Mercandelli;L. Bertulessi
2021-01-01

Abstract

This paper reviews state-of-the-art skew correction methods in time-interleaved (TI) analog-to-digital converters (ADCs) and introduces a novel mixed-signal skew correction technique based on dithering the control word of a digital-totime converter (DTC), which significantly relaxes the stringent DTC resolution requirements. Simulation results of a 10 GS/s 8– bit 16-core TI-ADC reveal that the proposed technique reduces the required DTC resolution by a factor of 4x and improves the spurious-free dynamic range (SFDR) by up to 10 dB with a negligible noise penalty.
2021
SMACD / PRIME 2021; International Conference on SMACD and 16th Conference on PRIME
9783800755882
ADC, SAR, CMOS, TI-ADC, DTC, Skew correction
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1186278
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