This paper presents a 28 nm CMOS 500 MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4 dB SNDR and 81.0 dB SFDR at 240 MHz input across PVT variations, consuming 6.64 mW with on-chip digital calibrations and occupying 0.011 mm2
11.3 A 500MS/s 12b Pipe-SAR ADC Using a Triple-Cascode FIA with Virtual Supply Extension
Michele Rocco;Gabriele Zanoletti;Alessia Ceroni;Giacomo Tombolan;Gabriele Be';Luca Ricci;Salvatore Levantino;Andrea Leonardo Lacaita;Luca Bertulessi;Carlo Samori;Andrea Giovanni Bonfanti
2026-01-01
Abstract
This paper presents a 28 nm CMOS 500 MS/s 12b three-stage pipeline SAR ADC based on a triple-cascode single-stage floating residue amplifier with virtual supply extension to improve its efficiency and linearity. The ADC achieves 63.4 dB SNDR and 81.0 dB SFDR at 240 MHz input across PVT variations, consuming 6.64 mW with on-chip digital calibrations and occupying 0.011 mm2File in questo prodotto:
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11.3_A_500MS_s_12b_Pipe-SAR_ADC_Using_a_Triple-Cascode_FIA_with_Virtual_Supply_Extension.pdf
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