A 20 MHz-BW 12.3-ENOB 3rd-Order Noise-Shaping SAR ADC with Multi-Input Architecture and PVT-Robust Ratio-Based FIA

Noise-shaping successive approximation register (NS-SAR) ADCs combine high resolution with energy efficiency, but their performance degrades at bandwidths in the tens of MHz due to limited oversampling ratios (OSR) and adoption of low-order passive filters. This work introduces a 3rd-order NS-SAR ADC that leverages a multi-input amplifier and a multiinput comparator, enabling independent optimization and flexible filter coefficient sizing. In addition, a ratio-based floating inverter amplifier ensures remarkable gain stability across process, voltage, and temperature (PVT) variations. Implemented in a 28-nm CMOS process, the prototype achieves 12.3-ENOB over a 20-MHz bandwidth while consuming 1.56 mW, resulting in a Schreier figure-of-merit (FoMS) of 177-dB with robust and consistent performance across PVT corners.