TESOLIN, FRANCESCO
TESOLIN, FRANCESCO
DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
2024-01-01 Rossoni, Michele; Dartizio, Simone Mattia; Tesolin, Francesco; Castoro, Giacomo; Dell'Orto, Riccardo; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
2024-01-01 Tesolin, Francesco; Dartizio, Simone Mattia; Castoro, Giacomo; Buccoleri, Francesco; Rossoni, Michele; Cherniak, Dmytro; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
2021-01-01 Santiccioli, A.; Mercandelli, M.; Dartizio, S. M.; Tesolin, F.; Karman, S.; Shehata, A.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
2023-01-01 Dartizio, Simone M.; Tesolin, Francesco; Castoro, Giacomo; Buccoleri, Francesco; Lanzoni, Luca; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
2023-01-01 Castoro, Giacomo; Dartizio, Simone M.; Tesolin, Francesco; Buccoleri, Francesco; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
2022-01-01 Dartizio, Simone M.; Tesolin, Francesco; Mercandelli, Mario; Santiccioli, Alessio; Shehata, Abanob; Karman, Saleh; Bertulessi, Luca; Buccoleri, Francesco; Avallone, Luca; Parisi, Angelo; Lacaita, Andrea L.; Kennedy, Michael P.; Samori, Carlo; Levantino, Salvatore
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
2021-01-01 Mercandelli, M.; Santiccioli, A.; Dartizio, S. M.; Shehata, A.; Tesolin, F.; Karman, S.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability
2021-01-01 Karman, S.; Tesolin, F.; Dago, A.; Mercandelli, M.; Samori, C.; Levantino, S.
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector
2024-01-01 Dartizio, S. M.; Rossoni, M.; Tesolin, F.; Castoro, G.; Samori, C.; Lacaita, A. L.; Levantino, S.
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC
2024-01-01 Salvi, Pietro; Dartizio, Simone M.; Rossoni, Michele; Tesolin, Francesco; Castoro, Giacomo; Lacaita, Andrea L.; Levantino, Salvatore
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
2022-01-01 Dartizio, S. M.; Buccoleri, F.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Iesurum, A.; Steffan, G.; Cherniak, D.; Bertulessi, L.; Bevilacqua, A.; Samori, C.; Lacaita, A. L.; Levantino, S.
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023-01-01 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
2024-01-01 Moleri, Riccardo; Dartizio, Simone Mattia; Rossoni, Michele; Castoro, Giacomo; Tesolin, Francesco; Cherniak, Dmytro; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
2022-01-01 Buccoleri, F.; Dartizio, S. M.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Lesurum, A.; Steffan, G.; Bevilacqua, A.; Bertulessi, L.; Cherniak, D.; Samori, C.; Lacaita, A. L.; Levantino, S.
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
2022-01-01 Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
2023-01-01 Dartizio, Sm; Tesolin, F; Castoro, G; Buccoleri, F; Rossoni, M; Cherniak, D; Samori, C; Lacaita, Al; Levantino, S
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
2023-01-01 Tesolin, Francesco; Dartizio, Simone M.; Buccoleri, Francesco; Santiccioli, Alessio; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A Novel Topology of Coupled Phase-Locked Loops
2021-01-01 Karman, Saleh; Tesolin, Francesco; Levantino, Salvatore; Samori, Carlo
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators
2021-01-01 Parisi, A.; Tesolin, F.; Mercandelli, M.; Bertulessi, L.; Lacaita, A. L.
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends
2021-01-01 Amendola, G.; Boccia, L.; Centurelli, F.; Chevalier, P.; Fonte, A.; Karman, S.; Levantino, S.; Mazzanti, A.; Mustacchio, C.; Pallotta, A.; Petricli, I.; Samori, C.; Tesolin, F.; Tommasino, P.; Traversa, A.; Trifiletti, A.