GALLUCCI, STEFANO
GALLUCCI, STEFANO
DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning
2025-01-01 Gallucci, Stefano; Tesolin, Francesco; Salvi, Pietro; Rizzini, Daniele Lodi; Moleri, Riccardo; Buccoleri, Francesco; Rossoni, Michele; Castoro, Giacomo; Dartizio, Simone Mattia; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
A -66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC
2026-01-01 Salvi, P.; Rossoni, M.; Moleri, R.; Lodi Rizzini, D.; Fagotti, D.; Gallucci, S.; Lacaita, A. L.; Dartizio, S. M.; Levantino, S.
A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS
2025-01-01 Dartizio, S. M.; Castoro, G.; Gallucci, S.; Rossoni, M.; Moleri, R.; Tesolin, F.; Salvi, P.; Karman, S.; Lacaita, A. L.; Levantino, S.
A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mVpp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning
2026-01-01 Gallucci, Stefano; Rizzini, Daniele Lodi; Moleri, Riccardo; Rossoni, Michele; Salvi, Pietro; Fagotti, Damiano; Tesolin, Franceso; Lacaita, Andrea Leonardo; Dartizio, Simone Mattia; Levantino, Salvatore
A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC
2025-01-01 Fagotti, D.; Dartizio, S. M.; Tesolin, F.; Moleri, R.; Trotta, G. R.; Rossoni, M.; Gallucci, S.; Salvi, P.; Castoro, G.; Lodi Rizzini, D.; Lacaita, A. L.; Levantino, S.
A DTC-Based Digital PLL Achieving –64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC
2026-01-01 Moleri, Riccardo; Rizzini, Daniele Lodi; Rossoni, Michele; Fagotti, Damiano; Salvi, Pietro; Gallucci, Stefano; Lacaita, Andrea Leonardo; Levantino, Salvatore; Dartizio, Simone Mattia
A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving -62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise
2026-01-01 Fagotti, D.; Moleri, R.; Rossoni, M.; Lodi Rizzini, D.; Salvi, P.; Gallucci, S.; Trotta, G. R.; Lacaita, A. L.; Dartizio, S. M.; Levantino, S.
A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple
2025-01-01 Rossoni, M.; Moleri, R.; Lodi Rizzini, D.; Salvi, P.; Gallucci, S.; Castoro, G.; Tesolin, F.; Lacaita, A. L.; Dartizio, S. M.; Levantino, S.
A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators
2025-01-01 Gallucci, Stefano; Tesolin, Francesco; Salvi, Pietro; Lodi Rizzini, Daniele; Moleri, Riccardo; Buccoleri, Francesco; Rossoni, Michele; Castoro, Giacomo; Samori, Carlo; Lacaita, Andrea Leonardo; Dartizio, Simone Mattia; Levantino, Salvatore