This work presents a fractional-N digital PLL achieving low-jitter by leveraging the combination of a XOR frequencydoubler and a power-efficient double-edge variable-slope digital-to-time converter (DTC). The prototype demonstrates 58.9fs jitter and -61.8 dBc fractional spur at 9.25 GHz, with 18.3 mW power and 125 MHz input reference frequency.
A 58.9fs-Jitter Fractional-N Digital PLL Using a Double-Edge Variable-Slope DTC
D. Fagotti;S. M. Dartizio;F. Tesolin;R. Moleri;G. R. Trotta;M. Rossoni;S. Gallucci;P. Salvi;G. Castoro;D. Lodi Rizzini;A. L. Lacaita;S. Levantino
2025-01-01
Abstract
This work presents a fractional-N digital PLL achieving low-jitter by leveraging the combination of a XOR frequencydoubler and a power-efficient double-edge variable-slope digital-to-time converter (DTC). The prototype demonstrates 58.9fs jitter and -61.8 dBc fractional spur at 9.25 GHz, with 18.3 mW power and 125 MHz input reference frequency.File in questo prodotto:
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A_58.9fs-Jitter_Fractional-N_Digital_PLL_Using_a_Double-Edge_Variable-Slope_DTC.pdf
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