A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector

To unlock wide data-rates, wireless transceivers require ultra-Iow-jitter local-oscillators. Fractional-N PLLs achieve low-noise using a digital-to-time converter (DTC) to re-align the edges of the reference and divider signals in fractional mode (Fig. 1 top) [1]. However, the PLL jitter is limited by both DTC non-linearity, causing large fractional spurs, and DTC jitter, degrading PLL in-band noise. Unfortunately, DTCs suffer from a strong trade-off between linearity, noise and power [2], [3]. The technique in [2] improves both DTC linearity and jitter by reducing the required DTC delay range, but it can only achieve 2x range reduction. This work introduces a digital PLL leveraging a multi-edge power-gating phase-detector (MEPG-PD) to reduce the required DTC range by more than 10x, It achieves 59. 3fs jitter and -62.1 dBc fractional spur at near-integer 8. 75GHz channels. Figure 1 (bottom left) describes the MEPG-PD concept. The MEPG-PO comprises a phase-detector (PO), generating the error signal e[k], fed to the PLL digital loop filter (DLF), and an auxiliary oscillator operating in power-gating mode (denoted as PGO) [4]. The divd signal, derived by delaying the PLL divider output, div, via the DTC, and the PGO output, OSCPG, are fed to the PD. At the rising edge of the PLL reference signal, ref, the PGO is turned on for a Tw time-window, by powering the PGO via a switch driven by the SWPG signal. If the PGO period, TPGO, is smaller than TW, OSCPG has multiple rising edges before the PGO turns off. In a conventional fractional-N PLL, the DTC re-aligns ref and div to achieve a zero PO input time-error, requiring a DTC delay of at least one period, Tdco, of the digitally-controlled-oscillator (DCO) at the PLL output. In the MEPG-PD scheme, instead, a zero time-error can be reached by aligning divd to the closest OSCPG rising edge, with a DTC delay of at most TPGC. By using TPGO < < Tdco, the DTC delay range and, correspondingly, its non-linearity and jitter, are drastically reduced. Note that the MEPG-PO non-linearity contribution is ideally zero, since the PGO edges are linearly spaced by TPGO, Furthermore, the PGO noise can be minimized using a small Tw, as shown later. However, to achieve a drastic DTC range reduction, the PGO must run at a frequency significantly higher than the DCO (e.g., 10x reduction requires a 100GHz PGO for a 10GHz DCO). To solve this issue, the MEPG-PD is instead implemented with three PDs and a PGO based on a 3-stage ring-oscillator (RO) (bottom right). The PDs are fed with divd and the three RO stage outputs, oscPG, 0, oscPG,1 and OSCPG,2. By aligning divd to the closest among tne rising ana failing edges of the RO outputs, the required DTC range reduces to TPGO/6, thus achieving the same range reduction at a 6x smaller PGO frequency (e.g., 10x reduction requires a 17GHz PGO for a 10GHz DCO). The PO selection logic provides the MEPG-PD error signal, e[k] selecting the output of the PO with zero-input time-error among the three.