RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

TESOLIN, FRANCESCO

TESOLIN, FRANCESCO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

Mostra records
Risultati 1 - 9 di 9 (tempo di esecuzione: 0.032 secondi).
Titolo Data di pubblicazione Autori File
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars 1-gen-2024 Tesolin, FrancescoDartizio, Simone M.Castoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 1-gen-2022 Simone M. DartizioFrancesco BuccoleriFrancesco TesolinAlessio SanticcioliDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore Levantino +
A Low-Jitter Fractional-$N$ Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC 1-gen-2024 Rossoni, MicheleDartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoDell'Orto, RiccardoLacaita, Andrea L.Levantino, Salvatore
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, SMTesolin, FCastoro, GBuccoleri, FRossoni, MCherniak, DSamori, CLacaita, ALLevantino, S
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2023 Tesolin, FrancescoDartizio, Simone M.Buccoleri, FrancescoSanticcioli, AlessioBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A Novel Topology of Coupled Phase-Locked Loops 1-gen-2021 Karman, SalehTesolin, FrancescoLevantino, SalvatoreSamori, Carlo
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 1-gen-2021 Parisi, A.Tesolin, F.Mercandelli, M.Bertulessi, L.Lacaita, A. L.