A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS

Ultra-low power (ULP) Bluetooth Low-Energy (BLE) transceivers (TRXs) are crucial for a wide range of battery-powered devices, including IoT nodes, sensors, and wearables. A BLE TRX should support GFSK modulation for BLE-packet transmission and adaptive frequency hopping (AFH), i.e., randomly jumping within the 2.402-to-2.480GHz BLE band, for minimizing interference from nearby wireless devices. Recently, digital-PLL (DPLL)-based GFSK modulators have gained traction for realizing ULP BLE TRXs [1-6]; however, achieving ULP, rapid frequency hopping, and low FSK error simultaneously remains challenging. A single-point modulated DPLL (Fig. 34.2.1 top-left) requires a wide BW [1], and, in turn, a wide-range time-to-digital converter (TDC) [2,3] and/or a high reference frequency [1]. Both these choices tend to degrade the PLL noise/power compromise and increase power dissipation. In contrast, a two-point modulated DPLL (top-right) can afford a narrow BW and a low reference frequency for low power dissipation but needs a large look-up table (LUT) to accurately estimate the DCO tuning curve for fast hopping [6]. However, the slow rate of the channel-hopping (CH) sequence (e.g., below 3kHz), compared to the GFSK symbol rate (e.g., 1MHz for BLE-1), makes the convergence of the LUT coefficients through LMS algorithms quite critical. In addition, in all cases, the design of an ULP DCO supporting GFSK and AFH is difficult due to the large number of switched-capacitor (SWcap) banks required to independently manage frequency modulation, hopping, and PVT spreads. Their capacitive load limits the maximum affordable tank-inductor value and the corresponding tank impedance, increasing the minimum bias current to reach a sufficient oscillation amplitude.