This work presents a 28-to-38 GHz frequency tripler in 55-nm SiGe BiCMOS technology. An on-chip background calibration technique maximizes the output power, improving the fundamental harmonic rejection over wide input-frequency and input-power variations. The implemented tripler, which occupies an area of 0.4 mm2 and dissipates a power of 54 mW, achieves more than 40-dB fundamental harmonic rejection across a 3-dB bandwidth of 10.2 GHz (30.3%) and over 13 dB of input-power variation.

A 28-38 GHz Digitally-Assisted Frequency Tripler with Background Calibration in 55nm SiGe BiCMOS

Lodi Rizzini, D.;Tesolin, F.;Rossoni, M.;Moleri, R.;Lacaita, A. L.;Dartizio, S. M.;Levantino, S.
2025-01-01

Abstract

This work presents a 28-to-38 GHz frequency tripler in 55-nm SiGe BiCMOS technology. An on-chip background calibration technique maximizes the output power, improving the fundamental harmonic rejection over wide input-frequency and input-power variations. The implemented tripler, which occupies an area of 0.4 mm2 and dissipates a power of 54 mW, achieves more than 40-dB fundamental harmonic rejection across a 3-dB bandwidth of 10.2 GHz (30.3%) and over 13 dB of input-power variation.
2025
2025 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
979-8-3315-1412-9
Background calibration, digital assistance, dithering, frequency multiplier, harmonic rejection
File in questo prodotto:
File Dimensione Formato  
A_28-38_GHz_Digitally-Assisted_Frequency_Tripler_with_Background_Calibration_in_55nm_SiGe_BiCMOS.pdf

Accesso riservato

Descrizione: Articolo
: Publisher’s version
Dimensione 1.93 MB
Formato Adobe PDF
1.93 MB Adobe PDF   Visualizza/Apri

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1294575
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 0
  • ???jsp.display-item.citation.isi??? ND
social impact