10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion

Improving the spatial resolution and reliability of target detection in CMOS FMCW radars is essential to facilitate the increased adoption of next generation fully autonomous driving vehicles. In this frame, digital PLLs using the two-point modulation (TPM) scheme (Fig. 10.6.1 top-left) are attractive solutions, thanks to their capability of generating fast and wide-bandwidth (BW) chirp modulations with short retrace time at low power, area, and phase noise [1–3]. Unfortunately, the non-linearity of the digitally controlled oscillator (DCO) degrades chirp linearity, generating significant spurs and triggering the detection of false targets. This issue combined with the existence of a trade-off between linearity and phase noise in the design of DCOs makes it difficult to further improve radar resolution. The piecewise-linear digital predistortion (PWL-DPD) mitigates DCO non-linearity [1, 4, 5] but has limited effectiveness in the case of non-smooth DCO tuning curves, such as that induced by the practical layout of a low-noise wide-range DCO. Substituting the DCO capacitor banks with a varactor driven by a DAC may be a solution [4, 5], but at the cost of a much larger power consumption; limited chirp slope and longer retrace time. To solve those limitations, this work introduces a non-uniform piecewise-parabolic digital predistortion (PWP-DPD), specifically designed to mitigate non-smooth DCO non-linearities. The implemented 10GHz PLL dissipates 21mW of power and achieves a phase noise of -116.5dBc/Hz at a 1MHz offset, as well as an rms frequency error below 150kHz when synthesizing sawtooth and triangular chirps at slope and bandwidth up to 680MHz/μs and 680MHz, respectively.