ROSSONI, MICHELE

ROSSONI, MICHELE  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 6 di 6 (tempo di esecuzione: 0.029 secondi).
Titolo Data di pubblicazione Autori File
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 1-gen-2024 Rossoni, MicheleDartizio, Simone MattiaTesolin, FrancescoCastoro, GiacomoDell'Orto, RiccardoSamori, CarloLacaita, Andrea LeonardoLevantino, Salvatore
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion 1-gen-2024 Tesolin, FrancescoDartizio, Simone MattiaCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleSamori, CarloLacaita, Andrea LeonardoLevantino, Salvatore +
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector 1-gen-2024 Dartizio S. M.Rossoni M.Tesolin F.Castoro G.Samori C.Lacaita A. L.Levantino S.
A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC 1-gen-2024 Salvi, PietroDartizio, Simone M.Rossoni, MicheleTesolin, FrancescoCastoro, GiacomoLacaita, Andrea L.Levantino, Salvatore