A 4.75GHz Digital PLL Achieving 30.4fs jitter under 5mVpp Supply Ripples Using a Voltage-Biased Oscillator with Adaptive Supply Sensitivity Cancellation and Common-Mode Resonance Tuning

An adaptive background calibration technique minimizing supply sensitivity and phase-noise in a voltage biased DCO is demonstrated in a 4.75-GHz digital PLL. The technique automatically minimizes DCO supply sensitivity, as well as DCO phase-noise in both flicker- and white-noise-dominated regions. The PLL prototype, implemented in 28nm CMOS, achieves 30.4-fs RMS jitter integrated from 10 kHz to 100 MHz, and a phase noise of –150.17 dBc/Hz at 10-MHz offset under 5mVpp sinusoidal supply disturbance.