A 10 GHz fractional-N digital PLL with a power-gated ring-oscillator (PGRO) to reduce digital-to-time converter (DTC) range and a PGRO-frequency-stabilizing loop to mitigate supply sensitivity is presented. The PLL achieves 74 fs and 81 fs rms jitter, when a 3mVpp sinusoid and a 2.5mVrms white noise are superimposed to the PGRO supply, respectively. © 2025 JSAP.
A Fractional-N Digital-PLL Based on a Power-Gated Ring-Oscillator and a Frequency-Stabilizing Loop Achieving 74fs Jitter Under 3mVpp Supply Ripple
M. Rossoni;R. Moleri;D. Lodi Rizzini;P. Salvi;S. Gallucci;G. Castoro;F. Tesolin;A. L. Lacaita;S. M. Dartizio;S. Levantino
2025-01-01
Abstract
A 10 GHz fractional-N digital PLL with a power-gated ring-oscillator (PGRO) to reduce digital-to-time converter (DTC) range and a PGRO-frequency-stabilizing loop to mitigate supply sensitivity is presented. The PLL achieves 74 fs and 81 fs rms jitter, when a 3mVpp sinusoid and a 2.5mVrms white noise are superimposed to the PGRO supply, respectively. © 2025 JSAP.File in questo prodotto:
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A_Fractional-N_Digital-PLL_Based_on_a_Power-Gated_Ring-Oscillator_and_a_Frequency-Stabilizing_Loop_Achieving_74fs_Jitter_Under_3_textmV_textpp_Supply_Ripple.pdf
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