A DTC-Based Digital PLL Achieving –64.5dBc Fractional Spur and 80fs Jitter with a 2-Track Probability-Density-Shaping ΔΣ Modulator and a Dithered-Threshold TDC

A fractional-N digital PLL employing a two-track probability-density-shaping ΔΣ modulator and a dithered-threshold TDC is presented. The first technique suppresses spurs arising from quadratic DTC nonlinearity while minimizing the required DTC delay range. The second technique mitigates spurs induced by TDC nonlinearity and enables accurate calibration of TDC resolution. The prototype achieves – 64.5dBc fractional spurs and 80fs jitter, representing the first DTC-based PLL using a stochastic ΔΣ modulator to achieve sub-100fs jitter.