A 28nm fractional-N digital PLL with a supply-insensitive variable-slope digital-to-time converter (DTC) is presented. Supply insensitivity is achieved by a background calibration loop, without affecting DTC linearity or noise. Measured results demonstrate 65.6fs jitter upon 6.2mVrms supply noise and <-62dBc spurs under 10mVpp supply-ripple over 10k-to-50MHz disturbance frequency range. The PLL covers 8.75-to-10.25GHz tuning range, while achieving a -251dB jitter-power figure of merit at 22.5mW power.
A Fractional-N Digital PLL with a Supply-Insensitive DTC Achieving -62dBc Spur and 69fs Jitter Under 10mVpp Sinusoidal DTC Supply Ripple and 6.2mVrms DTC Supply Noise
Fagotti D.;Moleri R.;Rossoni M.;Lodi Rizzini D.;Salvi P.;Gallucci S.;Trotta G. R.;Lacaita A. L.;Dartizio S. M.;Levantino S.
2026-01-01
Abstract
A 28nm fractional-N digital PLL with a supply-insensitive variable-slope digital-to-time converter (DTC) is presented. Supply insensitivity is achieved by a background calibration loop, without affecting DTC linearity or noise. Measured results demonstrate 65.6fs jitter upon 6.2mVrms supply noise and <-62dBc spurs under 10mVpp supply-ripple over 10k-to-50MHz disturbance frequency range. The PLL covers 8.75-to-10.25GHz tuning range, while achieving a -251dB jitter-power figure of merit at 22.5mW power.File in questo prodotto:
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A_Fractional-N_Digital_PLL_with_a_Supply-Insensitive_DTC_Achieving_62dBc_Spur_and_69fs_Jitter_Under_10mVpp_Sinusoidal_DTC_Supply_Ripple_and_6.2mVrms_DTC_Supply_Noise.pdf
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