This work presents a 10-to-12-GHz digital PLL employing a compact series-resonance oscillator to minimize out-of-band phase noise and an LC-based power-gated oscillator to suppress in-band noise and fractional spurs. Implemented in a 55-nm BiCMOS process, the PLL achieves RMS jitter of 14.9 fs and 25.4 fs at 11 GHz integer-N and near-integer fractional-N modes, respectively, while consuming 310 mW.
A 25.4 fs Jitter Fractional-N Digital PLL With an LC-Based Power-Gated Oscillator and Series-Resonance DCO
Rizzini, Daniele Lodi;Rossoni, Michele;Osio, Filippo;Gallucci, Stefano;Moleri, Riccardo;Lacaita, Andrea L.;Dartizio, Simone M.;Levantino, Salvatore
2026-01-01
Abstract
This work presents a 10-to-12-GHz digital PLL employing a compact series-resonance oscillator to minimize out-of-band phase noise and an LC-based power-gated oscillator to suppress in-band noise and fractional spurs. Implemented in a 55-nm BiCMOS process, the PLL achieves RMS jitter of 14.9 fs and 25.4 fs at 11 GHz integer-N and near-integer fractional-N modes, respectively, while consuming 310 mW.File in questo prodotto:
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