A fractional-N digital PLL adopting a pseudo-differential inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive blocks. The PLL achieves integrated jitter below 59fs under 10mVpp sinusoidal disturbance applied to the DTC supply in the fractional-N mode, with fractional spurs below -66dBc and the jitter-vs-power figure of merit of -251.4dB.
A -66dBc-Worst-Fractional-Spur and 58fs-Jitter Fractional-N Digital PLL Using a Supply-Resilient Pseudo-Differential Inverse-Constant-Slope DTC
Salvi P.;Rossoni M.;Moleri R.;Lodi Rizzini D.;Fagotti D.;Gallucci S.;Lacaita A. L.;Dartizio S. M.;Levantino S.
2026-01-01
Abstract
A fractional-N digital PLL adopting a pseudo-differential inverse-constant-slope DTC for rejection of supply disturbances is presented. Compared to traditional fractional-N digital PLLs, it requires no additional calibration for supply rejection or additional supply-insensitive blocks. The PLL achieves integrated jitter below 59fs under 10mVpp sinusoidal disturbance applied to the DTC supply in the fractional-N mode, with fractional spurs below -66dBc and the jitter-vs-power figure of merit of -251.4dB.File in questo prodotto:
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A_66dBc-Worst-Fractional-Spur_and_58fs-Jitter_Fractional-N_Digital_PLL_Using_a_Supply-Resilient_Pseudo-Differential_Inverse-Constant-Slope_DTC.pdf
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