LACAITA, ANDREA LEONARDO

LACAITA, ANDREA LEONARDO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Risultati 1 - 20 di 235 (tempo di esecuzione: 0.046 secondi).
Titolo Data di pubblicazione Autori File
"A Multistandard Σ-Δ Fractional-N Frequency Synthesizer for 802.11a/b/g WLAN" 1-gen-2007 BONFANTI, ANDREA GIOVANNISAMORI, CARLOLACAITA, ANDREA LEONARDO
"Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM" 1-gen-2007 IELMINI, DANIELECAGLI, CARLOLACAITA, ANDREA LEONARDO +
"Effects of the crystallization statistics on programming distributions in phase-change memory arrays" 1-gen-2007 IELMINI, DANIELELACAITA, ANDREA LEONARDO +
"Electrical characterization of anomalous cells in phase change memory arrays" 1-gen-2006 IELMINI, DANIELELACAITA, ANDREA LEONARDO +
"Geometry and material optimization for programming current scaling in phase-change memory" 1-gen-2007 IELMINI, DANIELELACAITA, ANDREA LEONARDO +
"Physical interpretation, modeling and impact on phase change memory (PCM) reliability of resistance drift due to chalcogenide structural relaxation" 1-gen-2007 IELMINI, DANIELELAVIZZARI, SIMONELACAITA, ANDREA LEONARDO +
"Reliability issues and scaling projections for phase change non volatile memories" 1-gen-2007 LACAITA, ANDREA LEONARDOIELMINI, DANIELE
"Status and challenges of PCM modeling" 1-gen-2007 LACAITA, ANDREA LEONARDOIELMINI, DANIELE
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM 1-gen-2024 Rossoni, MicheleDartizio, Simone MattiaTesolin, FrancescoCastoro, GiacomoDell'Orto, RiccardoSamori, CarloLacaita, Andrea LeonardoLevantino, Salvatore
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion 1-gen-2024 Tesolin, FrancescoDartizio, Simone MattiaCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleSamori, CarloLacaita, Andrea LeonardoLevantino, Salvatore +
13.5-mW, 5-GHz WLAN, CMOS frequency synthesizer using a true single phase clock divider 1-gen-2003 SAMORI, CARLOLEVANTINO, SALVATORELACAITA, ANDREA LEONARDO +
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 1-gen-2019 Grimaldi, LuigiBertulessi, LucaKarman, SalehSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
20 picosecond resolution single-photon solid-state detector 1-gen-1989 GHIONI, MASSIMO ANTONIOLACAITA, ANDREA LEONARDOCOVA, SERGIORIPAMONTI, GIANCARLO
20Mb/s Phase Modulator Based on a 3.6GHz Digital PLL with -36dB EVM at 5mW Power 1-gen-2012 MARZIN, GIOVANNILEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO
2D QM simulation and optimization of decanano non-overlapped MOS devices 1-gen-2003 GUSMEROLI, RICCARDOSOTTOCORNOLA SPINELLI, ALESSANDROPIROVANO, AGOSTINOLACAITA, ANDREA LEONARDO +
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning 1-gen-2025 Gallucci, StefanoTesolin, FrancescoSalvi, PietroRizzini, Daniele LodiMoleri, RiccardoBuccoleri, FrancescoRossoni, MicheleCastoro, GiacomoDartizio, Simone MattiaSamori, CarloLacaita, Andrea LeonardoLevantino, Salvatore
3D Monte Carlo simulation of the programming dynamics and their statistical variability in nanoscale charge-trap memories 1-gen-2010 AMOROSO, SALVATORE MARIAMACONI, ALESSANDROMONZIO COMPAGNONI, CHRISTIANSOTTOCORNOLA SPINELLI, ALESSANDROLACAITA, ANDREA LEONARDO +
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore