RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

LACAITA, ANDREA LEONARDO

LACAITA, ANDREA LEONARDO  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

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Titolo Data di pubblicazione Autori File
"Wireless Multi-Standard Terminals: System Analysis and Design of a Reconfigurable RF Front-end". 1-gen-2006 LACAITA, ANDREA LEONARDO +
20 ps timing resolution with single-photon avalanche diodes 1-gen-1989 COVA, SERGIOLACAITA, ANDREA LEONARDOGHIONI, MASSIMO ANTONIORIPAMONTI, GIANCARLO +
5-GHz Oscillator Array with Reduced Flicker Up-Conversion in 0.13-um CMOS 1-gen-2006 BONFANTI, ANDREA GIOVANNILEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli, AlessioMercandelli, MarioLacaita, Andrea L.Samori, CarloLevantino, Salvatore
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 1-gen-2015 LEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2022 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 13.5-mW 5-GHz Frequency Synthesizer with Dynamic Logic Frequency Divider 1-gen-2004 LEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
A 15-GHz Broad-Band ÷2 Frequency Divider in 0.13-µm CMOS Quadrature Generation. 1-gen-2005 BONFANTI, ANDREA GIOVANNITEDESCO, ANNAMARIASAMORI, CARLOLACAITA, ANDREA LEONARDO
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk In corso di stampa Ricci LucaGabriele Be'Michele RoccoScaletti LorenzoZanoletti GabrieleBertulessi LucaAndrea LacaitaLevantino SalvatoreSamori CarloBonfanti Andrea
A 2-V 2.5-GHz – 104-dBc/Hz at 100kHz Fully Integrated VCO with Wide-Band Low-Noise Automatic Amplitude Control Loop 1-gen-2001 SAMORI, CARLOLEVANTINO, SALVATORELACAITA, ANDREA LEONARDO +
A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power 1-gen-2011 TASCA, DAVIDEZANUSO, MARCOMARZIN, GIOVANNILEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power 1-gen-2012 MARZIN, GIOVANNILEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 6-fJ/conversion-step 200-kSps Asynchronous SAR ADC with Attenuation Capacitor in 130-nm CMOS adopting Standard MiM Capacitors 1-gen-2014 BRENNA, STEFANOBONFANTI, ANDREA GIOVANNILACAITA, ANDREA LEONARDO
A 64-Channel 965-μW Neural Recording SoC with UWB Wireless Transmission in 130-nm CMOS 1-gen-2016 Brenna, StefanoBONFANTI, ANDREA GIOVANNILACAITA, ANDREA LEONARDO +
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS 1-gen-2016 BONFANTI, ANDREA GIOVANNILACAITA, ANDREA LEONARDO +
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 1-gen-2022 Be' G.Bertulessi L.Ricci L.Scaletti L.Mercandelli M.Lacaita A. L.Levantino S.Samori C.Bonfanti A. +