MERCANDELLI, MARIO
MERCANDELLI, MARIO
DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
2021-01-01 Santiccioli, A.; Mercandelli, M.; Dartizio, S. M.; Tesolin, F.; Karman, S.; Shehata, A.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power
2019-01-01 Santiccioli, A.; Mercandelli, M.; Lacaita, A. L.; Samori, C.; Levantino, S.
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters
2022-01-01 Scaletti, Lorenzo; Be', Gabriele; Parisi, Angelo; Bertulessi, Luca; Ricci, Luca; Mercandelli, Mario; Levantino, Salvatore; Samori, Carlo; Bonfanti, ANDREA GIOVANNI
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
2020-01-01 Mercandelli, M.; Santiccioli, A.; Parisi, A.; Bertulessi, L.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S.
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
2021-01-01 Mercandelli, M.; Santiccioli, A.; Dartizio, S. M.; Shehata, A.; Tesolin, F.; Karman, S.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability
2021-01-01 Karman, S.; Tesolin, F.; Dago, A.; Mercandelli, M.; Samori, C.; Levantino, S.
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
2021-01-01 Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
2020-01-01 Santiccioli, A.; Mercandelli, M.; Bertulessi, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S.
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity
2021-01-01 Parisi, Angelo; Mercandelli, Mario; Samori, Carlo; Lacaita, ANDREA LEONARDO
A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter
2021-01-01 Be', G.; Mercandelli, M.; Bertulessi, L.