BERTULESSI, LUCA
BERTULESSI, LUCA
DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
2022-01-01 Mercandelli, Mario; Santiccioli, Alessio; Parisi, Angelo; Bertulessi, Luca; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
2022-01-01 Dartizio, Simone M.; Tesolin, Francesco; Mercandelli, Mario; Santiccioli, Alessio; Shehata, Abanob; Karman, Saleh; Bertulessi, Luca; Buccoleri, Francesco; Avallone, Luca; Parisi, Angelo; Lacaita, Andrea L.; Kennedy, Michael P.; Samori, Carlo; Levantino, Salvatore
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation
2018-01-01 Cherniak, Dmytro; Grimaldi, Luigi; Bertulessi, Luca; Nonis, Roberto; Samori, Carlo; Levantino, Salvatore
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization
2024-01-01 Zanoletti, Gabriele; Scaletti, Lorenzo; Be', Gabriele; Ricci, Luca; Rocco, Michele; Bertulessi, Luca; Samori, Carlo; Bonfanti, Andrea
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL
2020-01-01 Cherniak, Dmytro; Mercandelli, Mario; Bertulessi, Luca; Padovan, Fabio; Grimaldi, Luigi; Santiccioli, Alessio; Aichner, Michael; Samori, Carlo; Levantino, Salvatore
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
2019-01-01 Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking
2020-01-01 Santiccioli, Alessio; Mercandelli, Mario; Bertulessi, Luca; Parisi, Angelo; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023-01-01 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
2022-01-01 Be', G.; Parisi, A.; Bertulessi, L.; Ricci, L.; Scaletti, L.; Mercandelli, M.; Lacaita, A. L.; Levantino, S.; Samori, C.; Bonfanti, A.
A Background Calibration Technique to Control the Bandwidth of Digital PLLs
2018-01-01 Mercandelli, Mario; Grimaldi, Luigi; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A Digital PLL with Multi-tap LMS-based Bandwidth Control
2022-01-01 Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
2022-01-01 Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
2023-01-01 Tesolin, Francesco; Dartizio, Simone M.; Buccoleri, Francesco; Santiccioli, Alessio; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
2022-01-01 Bertulessi, Luca; Cherniak, Dmytro; Mercandelli, Mario; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators
2021-01-01 Parisi, A.; Tesolin, F.; Mercandelli, M.; Bertulessi, L.; Lacaita, A. L.