RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

BERTULESSI, LUCA

BERTULESSI, LUCA  

DIPARTIMENTO DI ELETTRONICA, INFORMAZIONE E BIOINGEGNERIA  

Mostra records
Risultati 1 - 16 di 16 (tempo di esecuzione: 0.019 secondi).
Titolo Data di pubblicazione Autori File
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2022 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk In corso di stampa Ricci LucaGabriele Be'Michele RoccoScaletti LorenzoZanoletti GabrieleBertulessi LucaAndrea LacaitaLevantino SalvatoreSamori CarloBonfanti Andrea
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization 1-gen-2024 Gabriele ZanolettiLorenzo ScalettiGabriele BeLuca RicciMichele RoccoLuca BertulessiCarlo SamoriAndrea Bonfanti
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 1-gen-2020 Mercandelli, MarioBertulessi, LucaSanticcioli, AlessioSamori, CarloLevantino, Salvatore +
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 1-gen-2022 Be' G.Bertulessi L.Ricci L.Scaletti L.Mercandelli M.Lacaita A. L.Levantino S.Samori C.Bonfanti A. +
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 1-gen-2018 MERCANDELLI, MARIOLuigi GrimaldiLuca BertulessiCarlo SamoriAndrea L. LacaitaSalvatore Levantino
A Digital PLL with Multi-tap LMS-based Bandwidth Control 1-gen-2022 Bertulessi, LucaSamori, CarloLevantino, Salvatore +
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 1-gen-2022 Simone M. DartizioFrancesco BuccoleriFrancesco TesolinAlessio SanticcioliDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore Levantino +
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2023 Tesolin, FrancescoDartizio, Simone M.Buccoleri, FrancescoSanticcioli, AlessioBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 1-gen-2022 Bertulessi, LucaMercandelli, MarioSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 1-gen-2021 Parisi, A.Tesolin, F.Mercandelli, M.Bertulessi, L.Lacaita, A. L.