A Wideband Digitally Assisted Frequency Tripler With Adaptively Optimized Output Power in 55-nm SiGe BiCMOS

This article presents a 28–38-GHz frequency tripler implemented in 55-nm SiGe BiCMOS technology with a novel on-chip background calibration technique. This technique continuously optimizes the circuit performance by maximizing output power and improving fundamental harmonic rejection. The proposed tripler achieves wideband operation and robust performance across varying operating conditions and input-power levels. The calibrated tripler demonstrates more than 40 dB of fundamental harmonic rejection and a 10.2-GHz (30.3%) 3-dB bandwidth. It occupies an area of 0.16 mm2 and consumes 54 mW of power. The results show the tripler maintains its performance over a 13-dB input-power variation, confirming the effectiveness of the proposed calibration method.