A Low Jitter and Low Spur Fractional-N Digital PLL Based on a DTC Chopping Technique

This work presents a digital-to-time converter (DTC)-based fractional-N digital phase-locked loop (PLL) designed to achieve simultaneously low jitter and low spurs. We introduce a novel DTC chopping technique that effectively mitigates fractional spurs, which we identify as predominantly arising from even-order nonlinearity invariable-slope (VS) DTCs. The proposed technique suppresses such spurs by randomly alternating the DTC position between the reference and divider signal paths. In addition, it proves effective in reducing the DTC flicker noise contribution. To ensure robust operation across process, voltage, and temperature (PVT) spreads, the design incorporates several background adaptive digital algorithms. Fabricated in a 28-nm CMOS process, the synthesizer occupies an active area of 0.22 mm2 and consumes 16.7 mW. At a 9.275-GHz near-integer channel, the measured worst case in-band fractional spur remains below −63 dBc, and the integrated rms jitter under 80 fs, yielding a jitter-power figure of merit (FoM) of −249.8 dB.