A Low-Noise Digital PLL With an Adaptive Common-Mode Resonance Tuning Technique for Voltage-Biased Oscillators

This work presents a digital phase-locked loop (PLL) incorporating an adaptive common-mode (CM) resonance tuning technique applied to a voltage-biased digitally-controlled oscillator (DCO). The method leverages the principle that the sensitivity of the oscillator frequency to a dither signal injected into the gate voltage of the cross-coupled transistors diminishes to near zero when the CM resonance is optimally tuned for minimal phase noise (PN). By detecting and nullifying this sensitivity, the proposed technique automatically adjusts the CM resonance to its ideal value. This background operation is continuous across the entire tuning range. The concept was validated through a digital PLL prototype fabricated in a 28-nm CMOS process, which achieved a jitter of 45.9 fs, a power-versus-jitter figure-of-merit of −257 dB, and a PN of −146.6 dBc/Hz at 10-MHz offset from a 4.75-GHz carrier, all within an active area of 0.21 mm2.