RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZONI, DAVIDE
 Distribuzione geografica
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Continente #
NA - Nord America 8.182
EU - Europa 5.361
AS - Asia 3.770
SA - Sud America 726
Continente sconosciuto - Info sul continente non disponibili 299
AF - Africa 188
OC - Oceania 10
Totale 18.536
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Nazione #
US - Stati Uniti d'America 7.980
IT - Italia 2.280
RU - Federazione Russa 1.469
SG - Singapore 1.069
CN - Cina 994
BR - Brasile 582
VN - Vietnam 543
DE - Germania 286
KR - Corea 264
HK - Hong Kong 223
FR - Francia 213
GB - Regno Unito 212
JP - Giappone 195
FI - Finlandia 155
ES - Italia 139
CA - Canada 122
AT - Austria 110
MA - Marocco 96
IN - India 95
NL - Olanda 91
SE - Svezia 76
BD - Bangladesh 68
ID - Indonesia 61
IE - Irlanda 61
AR - Argentina 59
PL - Polonia 56
UA - Ucraina 55
BE - Belgio 42
IQ - Iraq 37
TW - Taiwan 37
MX - Messico 34
CI - Costa d'Avorio 28
TR - Turchia 27
JO - Giordania 24
GR - Grecia 21
PK - Pakistan 21
CO - Colombia 20
ZA - Sudafrica 20
CH - Svizzera 19
EC - Ecuador 17
HR - Croazia 17
IR - Iran 14
VE - Venezuela 13
CL - Cile 11
LT - Lituania 11
AE - Emirati Arabi Uniti 10
PY - Paraguay 10
SA - Arabia Saudita 10
EG - Egitto 9
KZ - Kazakistan 9
PH - Filippine 9
CZ - Repubblica Ceca 8
IL - Israele 8
PE - Perù 8
RO - Romania 8
AU - Australia 7
JM - Giamaica 7
KE - Kenya 7
TH - Thailandia 7
UZ - Uzbekistan 7
CR - Costa Rica 6
MY - Malesia 6
DZ - Algeria 5
RS - Serbia 5
BZ - Belize 4
CU - Cuba 4
ET - Etiopia 4
LB - Libano 4
LV - Lettonia 4
NP - Nepal 4
TT - Trinidad e Tobago 4
AL - Albania 3
AO - Angola 3
BG - Bulgaria 3
DO - Repubblica Dominicana 3
GA - Gabon 3
GT - Guatemala 3
NZ - Nuova Zelanda 3
OM - Oman 3
PR - Porto Rico 3
PS - Palestinian Territory 3
TN - Tunisia 3
UY - Uruguay 3
AM - Armenia 2
BB - Barbados 2
BH - Bahrain 2
BY - Bielorussia 2
DK - Danimarca 2
EE - Estonia 2
GE - Georgia 2
HN - Honduras 2
KH - Cambogia 2
MD - Moldavia 2
MK - Macedonia 2
MN - Mongolia 2
MU - Mauritius 2
NI - Nicaragua 2
PA - Panama 2
QA - Qatar 2
SI - Slovenia 2
Totale 18.211
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Città #
Ashburn 1.514
Milan 1.234
Singapore 639
San Jose 580
Fairfield 564
Chandler 442
Woodbridge 346
Houston 248
Seoul 245
Seattle 237
Wilmington 236
Ann Arbor 231
Council Bluffs 202
Moscow 196
Hong Kong 190
Beijing 185
Cambridge 168
Santa Clara 168
Tokyo 166
Boardman 164
Los Angeles 146
The Dalles 142
Dallas 141
Hefei 141
Ho Chi Minh City 135
Helsinki 108
Hanoi 104
New York 103
Vienna 99
Lauterbourg 91
Dong Ket 76
Málaga 74
London 73
North Charleston 65
Rome 64
Buffalo 58
Medford 58
Lawrence 57
Ottawa 56
São Paulo 53
Dublin 51
Kenitra 48
Frankfurt am Main 47
Redwood City 46
Casablanca 45
Jakarta 44
Warsaw 43
Old Bridge 41
Columbus 40
Redmond 40
Dearborn 37
Guangzhou 37
Orem 37
Brussels 34
Phoenix 33
San Diego 31
Taipei 31
Shanghai 29
Abidjan 28
Brooklyn 28
Las Vegas 28
Brescia 26
Da Nang 26
Amsterdam 25
Chicago 25
Turin 25
Amman 24
Kent 24
Lucca 24
Erlangen 22
Rio de Janeiro 21
Barcelona 20
Buenos Aires 20
Haiphong 20
Livorno 20
Washington 20
Düsseldorf 19
Baghdad 18
Ceresara 18
Naples 18
Denver 17
Manchester 17
Miami 17
Munich 17
Norwalk 17
Zagreb 17
Atlanta 16
Belo Horizonte 16
Frisco 16
Lappeenranta 16
Montecassiano 16
Nuremberg 15
Des Moines 14
Jacksonville 14
Toronto 14
Falkenstein 13
Florence 13
Montreal 13
Mountain View 13
San Francisco 13
Totale 11.316
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Nome #
Design of side-channel resistant power monitors 540
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 448
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 355
Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach 346
An FPU design template to optimize the accuracy-efficiency-area trade-off 338
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 329
PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring 324
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 324
The TEXTAROSSA Project: Cool all the Way Down to the Hardware 311
Cost-effective fixed-point hardware support for RISC-V embedded systems 291
A survey on run-time power monitors at the edge 290
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 277
Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations 272
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems 268
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 268
All-digital energy-constrained controller for general-purpose accelerators and CPUs 267
On the use of hardware accelerators in QC-MDPC code-based cryptography 265
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 263
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 258
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures 257
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures 256
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 253
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 241
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems 236
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 232
PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation 232
Towards fine-grained DVFS in embedded multi-core CPUs 231
The TEXTAROSSA project: Cool all the Way Down to the Hardware 229
DENA: A DVFS-Capable Heterogeneous NoC Architecture 229
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 226
On the Effectiveness of True Random Number Generators Implemented on FPGAs 219
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 219
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 219
FPGA implementation of BIKE for quantum-resistant TLS 215
Consolidation of multi-tier workloads with performance and reliability constraints 215
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 214
A Control-Inspired Iterative Algorithm for Memory Management in NUMA Multicores 212
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 211
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 211
Enabling HPC for QoS-sensitive applications: The MANGO approach 207
Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis 205
A cycle accurate simulation framework for asynchronous NoC design 205
Analysis and countermeasures to side-channel attacks: a hardware design perspective 205
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 198
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments 197
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 190
Towards Energy-Efficient Functional Configuration in WSNs 190
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 188
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 188
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 187
An Accurate Simulation Framework for Thermal Explorations and Optimizations 184
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 184
A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures 182
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 181
A sensor-less NBTI mitigation methodology for NoC architectures 179
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 179
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 178
Integrating Side Channel Security in the FPGA Hardware Design Flow 177
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS 174
An analytical, dynamic, power-performance router model for run-time NoC optimizations 174
Una piattaforma informatica per prevenire attacchi ai canali laterali 171
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces 167
Thermal/performance trade-off in network-on-chip architectures 165
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 158
Heterogeneous Architectures and Networks-on-Chip Design and Simulation 158
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 157
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning 152
TEST: Assessing NoC policies facing aging and leakage power 148
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs 144
Sensor-wise methodology to face NBTI stress of NoC buffers 144
Monitor and Knob Techniques in Network-on-Chip Architectures 144
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs 140
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring 140
HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation 139
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators 135
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms 132
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-coherent NoCs 132
The MANGO FET-HPC project: An overview 127
Functional ISS-Driven Verification of Superscalar RISC-V Processors 126
Fast Estimations of Failure Probability Over Long Time Spans 126
Farmer: an online-learning driven methodology for workload consolidation on large fpgas 126
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research 114
Power-Efficient Software Allocation in Wireless Sensor Networks 113
Rabbit: Dynamic Clock Randomization to Protect Against Side-Channel Attacks 111
NBTI-aware design of NoC buffers 103
Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability 95
Rethinking the Switch Architecture for Stateful In-network Computing 91
Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support 82
Performance Implications at the Intersection of AF-XDP and Programmable NICs 75
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems 74
Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs 67
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration 23
DUA: Detection of Unrecognized Applications Using One-Class SVM in NoC-Based SoCs 14
Totale 18.536
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Categoria #
all - tutte 48.379
article - articoli 18.450
book - libri 0
conference - conferenze 27.555
curatela - curatele 0
other - altro 0
patent - brevetti 1.935
selected - selezionate 0
volume - volumi 439
Totale 96.758
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/2022760 0 59 111 51 45 42 28 52 57 88 132 95
2022/20231.201 107 110 55 180 101 134 18 78 170 102 74 72
2023/2024977 52 67 129 122 129 130 53 16 35 126 14 104
2024/20251.967 28 32 69 72 256 137 181 170 325 159 253 285
2025/20268.879 1.355 1.209 437 612 498 436 1.429 370 786 830 349 568
2026/2027906 412 494 0 0 0 0 0 0 0 0 0 0
Totale 18.536