RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZONI, DAVIDE
 Distribuzione geografica
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Continente #
NA - Nord America 5.756
EU - Europa 4.009
AS - Asia 2.142
SA - Sud America 642
AF - Africa 121
OC - Oceania 6
Totale 12.676
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Nazione #
US - Stati Uniti d'America 5.638
RU - Federazione Russa 1.465
IT - Italia 1.199
SG - Singapore 745
CN - Cina 621
BR - Brasile 531
VN - Vietnam 269
DE - Germania 265
GB - Regno Unito 182
FI - Finlandia 132
ES - Italia 124
FR - Francia 118
AT - Austria 109
KR - Corea 96
SE - Svezia 74
CA - Canada 73
HK - Hong Kong 66
NL - Olanda 60
ID - Indonesia 57
IE - Irlanda 56
IN - India 55
AR - Argentina 49
MA - Marocco 48
UA - Ucraina 47
PL - Polonia 44
JP - Giappone 43
BE - Belgio 40
MX - Messico 29
CI - Costa d'Avorio 28
IQ - Iraq 27
BD - Bangladesh 23
JO - Giordania 22
TR - Turchia 21
GR - Grecia 19
CH - Svizzera 17
ZA - Sudafrica 17
HR - Croazia 16
CO - Colombia 15
EC - Ecuador 15
PK - Pakistan 14
TW - Taiwan 10
IR - Iran 9
PE - Perù 8
PY - Paraguay 8
AE - Emirati Arabi Uniti 7
EG - Egitto 7
IL - Israele 7
KZ - Kazakistan 7
LT - Lituania 7
SA - Arabia Saudita 7
VE - Venezuela 7
CL - Cile 6
RO - Romania 6
CZ - Repubblica Ceca 5
KE - Kenya 5
DZ - Algeria 4
LB - Libano 4
RS - Serbia 4
UZ - Uzbekistan 4
AL - Albania 3
AO - Angola 3
AU - Australia 3
BZ - Belize 3
DO - Repubblica Dominicana 3
LV - Lettonia 3
NP - Nepal 3
NZ - Nuova Zelanda 3
PH - Filippine 3
TH - Thailandia 3
AM - Armenia 2
BG - Bulgaria 2
DK - Danimarca 2
EE - Estonia 2
GE - Georgia 2
KH - Cambogia 2
MY - Malesia 2
PA - Panama 2
PS - Palestinian Territory 2
QA - Qatar 2
SI - Slovenia 2
TN - Tunisia 2
TT - Trinidad e Tobago 2
UY - Uruguay 2
BB - Barbados 1
BH - Bahrain 1
BJ - Benin 1
BO - Bolivia 1
BY - Bielorussia 1
CR - Costa Rica 1
CY - Cipro 1
ET - Etiopia 1
GT - Guatemala 1
HN - Honduras 1
HU - Ungheria 1
JM - Giamaica 1
KG - Kirghizistan 1
LA - Repubblica Popolare Democratica del Laos 1
LK - Sri Lanka 1
LU - Lussemburgo 1
LY - Libia 1
Totale 12.666
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Città #
Ashburn 1.117
Fairfield 564
Singapore 448
Chandler 442
Milan 404
Woodbridge 346
Houston 239
Wilmington 236
Seattle 232
Ann Arbor 231
Moscow 196
Cambridge 168
Beijing 158
Hefei 141
Boardman 128
Santa Clara 115
Vienna 99
Dallas 98
Helsinki 85
Seoul 84
Council Bluffs 81
Dong Ket 76
Málaga 74
London 68
Los Angeles 64
Medford 58
Lawrence 57
Ottawa 56
Hong Kong 53
New York 50
Dublin 46
Redwood City 46
Casablanca 45
Buffalo 44
Ho Chi Minh City 44
Jakarta 44
Old Bridge 41
Redmond 40
São Paulo 40
Hanoi 39
Columbus 37
Dearborn 37
Frankfurt am Main 36
Brussels 33
Rome 32
Warsaw 31
San Diego 30
Abidjan 28
Brescia 24
Kent 24
Lucca 24
Amman 22
Erlangen 22
Livorno 20
Rio de Janeiro 20
Buenos Aires 19
Düsseldorf 19
Phoenix 19
Amsterdam 18
Brooklyn 18
Ceresara 18
Munich 17
Norwalk 17
Tokyo 17
Barcelona 16
Lappeenranta 16
Montecassiano 16
Washington 16
Zagreb 16
Baghdad 14
Chicago 14
Des Moines 13
Nuremberg 13
Orem 13
Shanghai 13
Belo Horizonte 12
Lauterbourg 12
Mountain View 12
Piacenza 12
Turin 12
Jacksonville 11
Miami 11
The Dalles 11
Athens 10
Bern 10
Brasília 10
Falkenstein 10
Haiphong 10
San Francisco 10
Curitiba 9
Fremont 9
Guarulhos 9
Napoli 9
Parma 9
Porto Alegre 9
Redondo Beach 9
Rovato 9
Salvador 9
Boston 8
Castel Mella 8
Totale 7.589
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Nome #
Design of side-channel resistant power monitors 477
Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach 301
PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring 290
An FPU design template to optimize the accuracy-efficiency-area trade-off 275
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 244
Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations 239
Cost-effective fixed-point hardware support for RISC-V embedded systems 227
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 225
A survey on run-time power monitors at the edge 221
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 220
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 217
All-digital energy-constrained controller for general-purpose accelerators and CPUs 215
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 214
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems 213
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 208
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures 206
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 202
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures 199
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 198
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 197
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems 192
Consolidation of multi-tier workloads with performance and reliability constraints 192
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 188
PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation 186
DENA: A DVFS-Capable Heterogeneous NoC Architecture 185
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 170
Enabling HPC for QoS-sensitive applications: The MANGO approach 169
A cycle accurate simulation framework for asynchronous NoC design 168
A Control-Inspired Iterative Algorithm for Memory Management in NUMA Multicores 168
On the Effectiveness of True Random Number Generators Implemented on FPGAs 167
Analysis and countermeasures to side-channel attacks: a hardware design perspective 167
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 164
On the use of hardware accelerators in QC-MDPC code-based cryptography 163
Towards fine-grained DVFS in embedded multi-core CPUs 161
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 159
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 156
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 151
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 149
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 147
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 143
Towards Energy-Efficient Functional Configuration in WSNs 142
FPGA implementation of BIKE for quantum-resistant TLS 141
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 141
An Accurate Simulation Framework for Thermal Explorations and Optimizations 140
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 135
An analytical, dynamic, power-performance router model for run-time NoC optimizations 134
Una piattaforma informatica per prevenire attacchi ai canali laterali 132
A sensor-less NBTI mitigation methodology for NoC architectures 131
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 129
TEST: Assessing NoC policies facing aging and leakage power 127
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments 127
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 127
Sensor-wise methodology to face NBTI stress of NoC buffers 126
Thermal/performance trade-off in network-on-chip architectures 126
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 126
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 124
Heterogeneous Architectures and Networks-on-Chip Design and Simulation 123
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces 121
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 112
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-coherent NoCs 111
Integrating Side Channel Security in the FPGA Hardware Design Flow 110
Monitor and Knob Techniques in Network-on-Chip Architectures 109
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators 108
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 107
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS 104
The MANGO FET-HPC project: An overview 104
HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation 104
A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures 101
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 98
Fast Estimations of Failure Probability Over Long Time Spans 98
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs 91
The TEXTAROSSA Project: Cool all the Way Down to the Hardware 90
Power-Efficient Software Allocation in Wireless Sensor Networks 88
Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis 86
NBTI-aware design of NoC buffers 86
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms 85
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring 85
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning 80
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 75
Functional ISS-Driven Verification of Superscalar RISC-V Processors 71
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs 70
Rabbit: Dynamic Clock Randomization to Protect Against Side-Channel Attacks 68
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research 68
Rethinking the Switch Architecture for Stateful In-network Computing 62
Farmer: an online-learning driven methodology for workload consolidation on large fpgas 44
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems 24
Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability 19
Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs 14
Performance Implications at the Intersection of AF-XDP and Programmable NICs 12
Totale 12.969
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Categoria #
all - tutte 37.632
article - articoli 14.342
book - libri 0
conference - conferenze 21.349
curatela - curatele 0
other - altro 0
patent - brevetti 1.589
selected - selezionate 0
volume - volumi 352
Totale 75.264
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021698 0 0 0 0 0 101 48 36 97 102 70 244
2021/2022819 59 59 111 51 45 42 28 52 57 88 132 95
2022/20231.201 107 110 55 180 101 134 18 78 170 102 74 72
2023/2024977 52 67 129 122 129 130 53 16 35 126 14 104
2024/20251.967 28 32 69 72 256 137 181 170 325 159 253 285
2025/20264.218 1.355 1.209 437 612 498 107 0 0 0 0 0 0
Totale 12.969