RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZONI, DAVIDE
 Distribuzione geografica
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Continente #
NA - Nord America 7.614
EU - Europa 5.237
AS - Asia 3.728
SA - Sud America 725
AF - Africa 188
OC - Oceania 10
Totale 17.502
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Nazione #
US - Stati Uniti d'America 7.439
IT - Italia 2.159
RU - Federazione Russa 1.469
SG - Singapore 1.057
CN - Cina 991
BR - Brasile 581
VN - Vietnam 542
DE - Germania 286
KR - Corea 261
HK - Hong Kong 217
FR - Francia 213
GB - Regno Unito 212
JP - Giappone 194
FI - Finlandia 154
ES - Italia 138
AT - Austria 110
CA - Canada 108
MA - Marocco 96
NL - Olanda 91
IN - India 89
SE - Svezia 76
ID - Indonesia 61
IE - Irlanda 61
AR - Argentina 59
BD - Bangladesh 59
PL - Polonia 55
UA - Ucraina 55
BE - Belgio 42
IQ - Iraq 37
TW - Taiwan 37
MX - Messico 34
CI - Costa d'Avorio 28
TR - Turchia 27
JO - Giordania 24
GR - Grecia 21
CO - Colombia 20
PK - Pakistan 20
ZA - Sudafrica 20
CH - Svizzera 19
EC - Ecuador 17
HR - Croazia 17
IR - Iran 14
VE - Venezuela 13
CL - Cile 11
LT - Lituania 11
AE - Emirati Arabi Uniti 10
PY - Paraguay 10
SA - Arabia Saudita 10
EG - Egitto 9
KZ - Kazakistan 9
PH - Filippine 9
CZ - Repubblica Ceca 8
IL - Israele 8
PE - Perù 8
RO - Romania 8
AU - Australia 7
KE - Kenya 7
TH - Thailandia 7
UZ - Uzbekistan 7
MY - Malesia 6
DZ - Algeria 5
RS - Serbia 5
BZ - Belize 4
CR - Costa Rica 4
CU - Cuba 4
ET - Etiopia 4
JM - Giamaica 4
LB - Libano 4
LV - Lettonia 4
NP - Nepal 4
AL - Albania 3
AO - Angola 3
BG - Bulgaria 3
DO - Repubblica Dominicana 3
GA - Gabon 3
NZ - Nuova Zelanda 3
OM - Oman 3
PS - Palestinian Territory 3
TN - Tunisia 3
TT - Trinidad e Tobago 3
UY - Uruguay 3
AM - Armenia 2
BB - Barbados 2
BH - Bahrain 2
BY - Bielorussia 2
DK - Danimarca 2
EE - Estonia 2
GE - Georgia 2
KH - Cambogia 2
MD - Moldavia 2
MK - Macedonia 2
MN - Mongolia 2
MU - Mauritius 2
NI - Nicaragua 2
PA - Panama 2
QA - Qatar 2
SI - Slovenia 2
SV - El Salvador 2
UG - Uganda 2
BJ - Benin 1
Totale 17.480
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Città #
Ashburn 1.456
Milan 1.129
Singapore 632
San Jose 571
Fairfield 564
Chandler 442
Woodbridge 346
Houston 246
Seoul 245
Wilmington 236
Seattle 234
Ann Arbor 231
Moscow 196
Hong Kong 187
Beijing 184
Cambridge 168
Tokyo 165
Boardman 164
Santa Clara 151
The Dalles 142
Council Bluffs 141
Hefei 141
Dallas 140
Ho Chi Minh City 134
Los Angeles 127
Helsinki 107
Hanoi 104
Vienna 99
Lauterbourg 91
New York 87
Dong Ket 76
Málaga 74
London 73
Rome 63
Medford 58
Lawrence 57
Ottawa 56
Buffalo 55
São Paulo 52
Dublin 51
Kenitra 48
Frankfurt am Main 47
Redwood City 46
Casablanca 45
Jakarta 44
North Charleston 43
Warsaw 42
Old Bridge 41
Redmond 40
Columbus 39
Dearborn 37
Guangzhou 37
Orem 37
Brussels 34
San Diego 31
Taipei 31
Shanghai 29
Abidjan 28
Brooklyn 26
Da Nang 26
Amsterdam 25
Amman 24
Brescia 24
Kent 24
Lucca 24
Turin 24
Chicago 23
Erlangen 22
Phoenix 22
Las Vegas 21
Rio de Janeiro 21
Barcelona 20
Buenos Aires 20
Haiphong 20
Livorno 20
Washington 20
Düsseldorf 19
Baghdad 18
Ceresara 18
Manchester 17
Miami 17
Munich 17
Norwalk 17
Zagreb 17
Belo Horizonte 16
Lappeenranta 16
Montecassiano 16
Denver 15
Naples 15
Nuremberg 15
Des Moines 14
Jacksonville 14
Falkenstein 13
Florence 13
Frisco 13
Toronto 13
Mountain View 12
Piacenza 12
Atlanta 11
Montreal 11
Totale 10.939
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Nome #
Design of side-channel resistant power monitors 531
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 415
Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach 345
An FPU design template to optimize the accuracy-efficiency-area trade-off 335
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 328
PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring 320
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 316
A survey on run-time power monitors at the edge 284
The TEXTAROSSA Project: Cool all the Way Down to the Hardware 283
Cost-effective fixed-point hardware support for RISC-V embedded systems 283
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 274
Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations 269
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems 267
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 264
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 262
All-digital energy-constrained controller for general-purpose accelerators and CPUs 260
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 255
On the use of hardware accelerators in QC-MDPC code-based cryptography 255
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 250
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures 249
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures 244
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 240
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems 234
PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation 229
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 228
DENA: A DVFS-Capable Heterogeneous NoC Architecture 227
Towards fine-grained DVFS in embedded multi-core CPUs 226
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 224
On the Effectiveness of True Random Number Generators Implemented on FPGAs 217
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 214
Consolidation of multi-tier workloads with performance and reliability constraints 213
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 212
FPGA implementation of BIKE for quantum-resistant TLS 211
A Control-Inspired Iterative Algorithm for Memory Management in NUMA Multicores 211
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 207
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 206
Enabling HPC for QoS-sensitive applications: The MANGO approach 204
Analysis and countermeasures to side-channel attacks: a hardware design perspective 204
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 200
A cycle accurate simulation framework for asynchronous NoC design 198
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments 192
Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis 190
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 190
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 189
Towards Energy-Efficient Functional Configuration in WSNs 188
The TEXTAROSSA project: Cool all the Way Down to the Hardware 187
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 185
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 184
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 184
An Accurate Simulation Framework for Thermal Explorations and Optimizations 183
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 182
A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures 179
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 178
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 177
A sensor-less NBTI mitigation methodology for NoC architectures 174
An analytical, dynamic, power-performance router model for run-time NoC optimizations 172
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 171
Una piattaforma informatica per prevenire attacchi ai canali laterali 169
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS 165
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces 163
Integrating Side Channel Security in the FPGA Hardware Design Flow 163
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 156
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 156
Heterogeneous Architectures and Networks-on-Chip Design and Simulation 155
Thermal/performance trade-off in network-on-chip architectures 154
TEST: Assessing NoC policies facing aging and leakage power 147
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning 144
Sensor-wise methodology to face NBTI stress of NoC buffers 143
Monitor and Knob Techniques in Network-on-Chip Architectures 141
HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation 137
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs 135
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring 135
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators 133
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs 131
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-coherent NoCs 131
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms 129
The MANGO FET-HPC project: An overview 126
Fast Estimations of Failure Probability Over Long Time Spans 125
Functional ISS-Driven Verification of Superscalar RISC-V Processors 123
Farmer: an online-learning driven methodology for workload consolidation on large fpgas 123
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 121
Power-Efficient Software Allocation in Wireless Sensor Networks 113
Rabbit: Dynamic Clock Randomization to Protect Against Side-Channel Attacks 104
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research 102
NBTI-aware design of NoC buffers 102
Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability 90
Rethinking the Switch Architecture for Stateful In-network Computing 89
Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support 75
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems 70
Performance Implications at the Intersection of AF-XDP and Programmable NICs 66
Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs 62
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration 20
DUA: Detection of Unrecognized Applications Using One-Class SVM in NoC-Based SoCs 4
Totale 17.801
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Categoria #
all - tutte 46.286
article - articoli 17.554
book - libri 0
conference - conferenze 26.436
curatela - curatele 0
other - altro 0
patent - brevetti 1.872
selected - selezionate 0
volume - volumi 424
Totale 92.572
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2021/2022819 59 59 111 51 45 42 28 52 57 88 132 95
2022/20231.201 107 110 55 180 101 134 18 78 170 102 74 72
2023/2024977 52 67 129 122 129 130 53 16 35 126 14 104
2024/20251.967 28 32 69 72 256 137 181 170 325 159 253 285
2025/20268.879 1.355 1.209 437 612 498 436 1.429 370 786 830 349 568
2026/2027171 171 0 0 0 0 0 0 0 0 0 0 0
Totale 17.801