RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZONI, DAVIDE
 Distribuzione geografica
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Continente #
NA - Nord America 4.241
EU - Europa 1.946
AS - Asia 441
AF - Africa 26
SA - Sud America 11
OC - Oceania 3
Totale 6.668
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Nazione #
US - Stati Uniti d'America 4.178
IT - Italia 986
DE - Germania 157
GB - Regno Unito 147
VN - Vietnam 144
FI - Finlandia 113
ES - Italia 107
AT - Austria 92
SG - Singapore 89
SE - Svezia 67
CN - Cina 65
CA - Canada 59
IE - Irlanda 52
FR - Francia 50
UA - Ucraina 40
BE - Belgio 32
JP - Giappone 31
IN - India 28
PL - Polonia 25
CI - Costa d'Avorio 22
JO - Giordania 18
GR - Grecia 17
HR - Croazia 16
HK - Hong Kong 15
CH - Svizzera 14
NL - Olanda 12
KR - Corea 11
TR - Turchia 9
ID - Indonesia 7
BR - Brasile 5
RU - Federazione Russa 5
TW - Taiwan 5
IL - Israele 4
IR - Iran 4
AR - Argentina 3
BZ - Belize 3
CZ - Repubblica Ceca 3
BG - Bulgaria 2
EG - Egitto 2
LB - Libano 2
LT - Lituania 2
MY - Malesia 2
NZ - Nuova Zelanda 2
PE - Perù 2
QA - Qatar 2
RS - Serbia 2
SI - Slovenia 2
AO - Angola 1
AU - Australia 1
BJ - Benin 1
CL - Cile 1
LA - Repubblica Popolare Democratica del Laos 1
LK - Sri Lanka 1
LU - Lussemburgo 1
MD - Moldavia 1
MX - Messico 1
PK - Pakistan 1
RO - Romania 1
SY - Repubblica araba siriana 1
TH - Thailandia 1
Totale 6.668
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Città #
Fairfield 564
Ashburn 551
Chandler 442
Woodbridge 346
Milan 301
Wilmington 235
Houston 233
Ann Arbor 231
Seattle 225
Cambridge 168
Vienna 90
Helsinki 83
Dong Ket 76
Málaga 74
London 64
Medford 58
Lawrence 57
Ottawa 56
Boardman 55
Singapore 49
Redwood City 46
Beijing 42
Dublin 42
Dallas 41
Old Bridge 41
Redmond 40
Dearborn 37
Brussels 32
Columbus 28
San Diego 28
Rome 25
Lucca 24
Abidjan 22
New York 22
Livorno 20
Brescia 19
Amman 18
Ceresara 18
Norwalk 17
Warsaw 17
Montecassiano 16
Washington 16
Zagreb 16
Des Moines 13
Mountain View 12
Piacenza 12
Barcelona 11
Jacksonville 11
Bern 10
Miami 10
Phoenix 10
Falkenstein 9
Fremont 9
Napoli 9
Parma 9
Rovato 9
Turin 9
Athens 8
Castel Mella 8
Cortenuova 8
Hong Kong 8
Lonato 8
Teglio 8
Brooklyn 7
Monza 7
Amsterdam 6
Braunschweig 6
Cavenago Di Brianza 6
Cremona 6
Florence 6
Jesi 6
Tokyo 6
Vedano al Lambro 6
Bologna 5
Chicago 5
Coccaglio 5
Hanoi 5
Jakarta 5
Kutno 5
Mantova 5
Nuremberg 5
Paris 5
Bergamo 4
Girona 4
Lappeenranta 4
Madrid 4
Mumbai 4
Nürnberg 4
San Francisco 4
San Jose 4
Torre Annunziata 4
Atlanta 3
Bangalore 3
Belize City 3
Berlin 3
Besana in Brianza 3
Calcinate 3
Cincinnati 3
Clayton 3
Cupertino 3
Totale 4.946
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Nome #
Design of side-channel resistant power monitors 342
PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring 226
Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach 210
An FPU design template to optimize the accuracy-efficiency-area trade-off 196
Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations 161
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 157
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 153
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 150
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems 150
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures 144
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 142
All-digital energy-constrained controller for general-purpose accelerators and CPUs 140
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 135
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 134
PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation 134
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 132
Cost-effective fixed-point hardware support for RISC-V embedded systems 132
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures 130
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 127
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 124
Analysis and countermeasures to side-channel attacks: a hardware design perspective 123
Consolidation of multi-tier workloads with performance and reliability constraints 121
DENA: A DVFS-Capable Heterogeneous NoC Architecture 120
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 117
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems 116
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 115
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 110
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 109
Sensor-wise methodology to face NBTI stress of NoC buffers 100
Enabling HPC for QoS-sensitive applications: The MANGO approach 100
Towards Energy-Efficient Functional Configuration in WSNs 99
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 99
Towards fine-grained DVFS in embedded multi-core CPUs 97
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 96
Una piattaforma informatica per prevenire attacchi ai canali laterali 96
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 93
A Control-Inspired Iterative Algorithm for Memory Management in NUMA Multicores 92
Thermal/performance trade-off in network-on-chip architectures 91
A cycle accurate simulation framework for asynchronous NoC design 89
An analytical, dynamic, power-performance router model for run-time NoC optimizations 88
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-coherent NoCs 83
An Accurate Simulation Framework for Thermal Explorations and Optimizations 82
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 82
The MANGO FET-HPC project: An overview 81
Monitor and Knob Techniques in Network-on-Chip Architectures 78
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators 77
On the use of hardware accelerators in QC-MDPC code-based cryptography 77
TEST: Assessing NoC policies facing aging and leakage power 76
Heterogeneous Architectures and Networks-on-Chip Design and Simulation 70
A sensor-less NBTI mitigation methodology for NoC architectures 70
Fast Estimations of Failure Probability Over Long Time Spans 70
NBTI-aware design of NoC buffers 65
Integrating Side Channel Security in the FPGA Hardware Design Flow 62
On the Effectiveness of True Random Number Generators Implemented on FPGAs 61
A survey on run-time power monitors at the edge 59
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 57
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 54
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 47
Power-Efficient Software Allocation in Wireless Sensor Networks 42
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments 42
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 40
HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation 40
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 40
FPGA implementation of BIKE for quantum-resistant TLS 39
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 34
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 33
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 28
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 24
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces 14
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 8
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 8
Totale 6.933
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Categoria #
all - tutte 22.035
article - articoli 8.936
book - libri 0
conference - conferenze 11.917
curatela - curatele 0
other - altro 0
patent - brevetti 937
selected - selezionate 0
volume - volumi 245
Totale 44.070
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20201.097 0 0 0 84 142 133 173 126 139 92 124 84
2020/20211.187 87 61 96 69 176 101 48 36 97 102 70 244
2021/2022819 59 59 111 51 45 42 28 52 57 88 132 95
2022/20231.201 107 110 55 180 101 134 18 78 170 102 74 72
2023/2024977 52 67 129 122 129 130 53 16 35 126 14 104
2024/2025149 28 32 69 20 0 0 0 0 0 0 0 0
Totale 6.933