RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ZONI, DAVIDE
 Distribuzione geografica
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Continente #
NA - Nord America 7.255
EU - Europa 4.742
AS - Asia 3.657
SA - Sud America 720
AF - Africa 188
OC - Oceania 10
Totale 16.572
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Nazione #
US - Stati Uniti d'America 7.107
IT - Italia 1.680
RU - Federazione Russa 1.469
SG - Singapore 1.048
CN - Cina 985
BR - Brasile 579
VN - Vietnam 523
DE - Germania 286
KR - Corea 259
HK - Hong Kong 216
FR - Francia 212
GB - Regno Unito 211
JP - Giappone 194
FI - Finlandia 154
ES - Italia 138
AT - Austria 110
MA - Marocco 96
CA - Canada 88
IN - India 84
NL - Olanda 80
SE - Svezia 76
ID - Indonesia 61
IE - Irlanda 60
AR - Argentina 58
PL - Polonia 55
UA - Ucraina 55
BE - Belgio 41
IQ - Iraq 37
TW - Taiwan 36
MX - Messico 33
BD - Bangladesh 32
CI - Costa d'Avorio 28
TR - Turchia 27
JO - Giordania 24
GR - Grecia 21
PK - Pakistan 20
ZA - Sudafrica 20
CH - Svizzera 19
CO - Colombia 18
EC - Ecuador 17
HR - Croazia 17
IR - Iran 14
VE - Venezuela 13
CL - Cile 11
LT - Lituania 11
PY - Paraguay 10
SA - Arabia Saudita 10
AE - Emirati Arabi Uniti 9
EG - Egitto 9
KZ - Kazakistan 9
PH - Filippine 9
CZ - Repubblica Ceca 8
IL - Israele 8
PE - Perù 8
RO - Romania 8
AU - Australia 7
KE - Kenya 7
TH - Thailandia 7
UZ - Uzbekistan 7
MY - Malesia 6
DZ - Algeria 5
RS - Serbia 5
CR - Costa Rica 4
CU - Cuba 4
ET - Etiopia 4
LB - Libano 4
LV - Lettonia 4
NP - Nepal 4
AL - Albania 3
AO - Angola 3
BG - Bulgaria 3
BZ - Belize 3
DO - Repubblica Dominicana 3
GA - Gabon 3
NZ - Nuova Zelanda 3
OM - Oman 3
PS - Palestinian Territory 3
TN - Tunisia 3
UY - Uruguay 3
AM - Armenia 2
BB - Barbados 2
BH - Bahrain 2
BY - Bielorussia 2
DK - Danimarca 2
EE - Estonia 2
GE - Georgia 2
JM - Giamaica 2
KH - Cambogia 2
MD - Moldavia 2
MK - Macedonia 2
MN - Mongolia 2
MU - Mauritius 2
NI - Nicaragua 2
PA - Panama 2
QA - Qatar 2
SI - Slovenia 2
TT - Trinidad e Tobago 2
UG - Uganda 2
BJ - Benin 1
BO - Bolivia 1
Totale 16.552
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Città #
Ashburn 1.424
Milan 838
Singapore 626
Fairfield 564
San Jose 560
Chandler 442
Woodbridge 346
Seoul 245
Houston 243
Wilmington 236
Seattle 233
Ann Arbor 231
Moscow 196
Hong Kong 186
Beijing 179
Cambridge 168
Tokyo 165
Hefei 141
The Dalles 141
Dallas 138
Council Bluffs 136
Boardman 130
Santa Clara 128
Ho Chi Minh City 124
Los Angeles 124
Helsinki 107
Vienna 99
Hanoi 97
Lauterbourg 91
New York 82
Dong Ket 76
Málaga 74
London 73
Medford 58
Lawrence 57
Ottawa 56
Buffalo 51
Dublin 50
São Paulo 50
Kenitra 48
Frankfurt am Main 47
Redwood City 46
Casablanca 45
Jakarta 44
North Charleston 43
Old Bridge 41
Warsaw 41
Redmond 40
Columbus 39
Dearborn 37
Guangzhou 37
Orem 37
Rome 35
Brussels 33
Taipei 31
San Diego 30
Abidjan 28
Shanghai 28
Da Nang 26
Amsterdam 25
Amman 24
Brescia 24
Kent 24
Lucca 24
Erlangen 22
Phoenix 22
Chicago 21
Rio de Janeiro 21
Barcelona 20
Brooklyn 20
Buenos Aires 20
Haiphong 20
Las Vegas 20
Livorno 20
Düsseldorf 19
Baghdad 18
Ceresara 18
Munich 17
Norwalk 17
Washington 17
Zagreb 17
Belo Horizonte 16
Lappeenranta 16
Manchester 16
Montecassiano 16
Nuremberg 15
Turin 15
Denver 14
Des Moines 14
Miami 14
Falkenstein 13
Jacksonville 12
Mountain View 12
Piacenza 12
Shenzhen 11
Tianjin 11
Athens 10
Bern 10
Brasília 10
Chennai 10
Totale 10.418
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Nome #
Design of side-channel resistant power monitors 522
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 356
Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach 343
An FPU design template to optimize the accuracy-efficiency-area trade-off 325
PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring 319
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 307
A survey on run-time power monitors at the edge 276
Cost-effective fixed-point hardware support for RISC-V embedded systems 271
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 270
Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations 267
CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties 261
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 260
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations 257
MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems 256
All-digital energy-constrained controller for general-purpose accelerators and CPUs 256
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 253
On the use of hardware accelerators in QC-MDPC code-based cryptography 249
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS 248
A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures 246
A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures 239
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 227
PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation 225
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 222
The TEXTAROSSA Project: Cool all the Way Down to the Hardware 221
BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers 221
DENA: A DVFS-Capable Heterogeneous NoC Architecture 221
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems 220
On the Effectiveness of True Random Number Generators Implemented on FPGAs 211
Consolidation of multi-tier workloads with performance and reliability constraints 208
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 206
Towards fine-grained DVFS in embedded multi-core CPUs 205
A Control-Inspired Iterative Algorithm for Memory Management in NUMA Multicores 204
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 204
FPGA implementation of BIKE for quantum-resistant TLS 202
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 201
Enabling HPC for QoS-sensitive applications: The MANGO approach 198
Analysis and countermeasures to side-channel attacks: a hardware design perspective 196
A cycle accurate simulation framework for asynchronous NoC design 194
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 194
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 188
CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs 183
Towards Energy-Efficient Functional Configuration in WSNs 183
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 182
An Accurate Simulation Framework for Thermal Explorations and Optimizations 179
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 178
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 178
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments 178
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 175
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 174
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 173
A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures 171
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 168
An analytical, dynamic, power-performance router model for run-time NoC optimizations 165
A sensor-less NBTI mitigation methodology for NoC architectures 164
Una piattaforma informatica per prevenire attacchi ai canali laterali 163
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS 159
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces 159
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 158
Integrating Side Channel Security in the FPGA Hardware Design Flow 157
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 154
Thermal/performance trade-off in network-on-chip architectures 152
Heterogeneous Architectures and Networks-on-Chip Design and Simulation 146
TEST: Assessing NoC policies facing aging and leakage power 146
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 141
Sensor-wise methodology to face NBTI stress of NoC buffers 140
Monitor and Knob Techniques in Network-on-Chip Architectures 137
Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis 135
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning 135
HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation 135
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs 131
Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators 130
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-coherent NoCs 130
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring 128
The MANGO FET-HPC project: An overview 126
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms 125
The TEXTAROSSA project: Cool all the Way Down to the Hardware 123
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs 119
Fast Estimations of Failure Probability Over Long Time Spans 117
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 117
Functional ISS-Driven Verification of Superscalar RISC-V Processors 114
Power-Efficient Software Allocation in Wireless Sensor Networks 111
Farmer: an online-learning driven methodology for workload consolidation on large fpgas 104
NBTI-aware design of NoC buffers 101
Rabbit: Dynamic Clock Randomization to Protect Against Side-Channel Attacks 96
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research 96
Rethinking the Switch Architecture for Stateful In-network Computing 86
Non-Functional Properties in HPC Systems: Design Exploration of Energy, Power, and Reliability 80
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems 62
Performance Implications at the Intersection of AF-XDP and Programmable NICs 57
Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs 49
Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support 42
FARMER: Online-Learning-Based Workload Consolidation on Large FPGAs Accelerated With Dynamic Partial Reconfiguration 9
Totale 16.870
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Categoria #
all - tutte 43.845
article - articoli 16.627
book - libri 0
conference - conferenze 24.999
curatela - curatele 0
other - altro 0
patent - brevetti 1.806
selected - selezionate 0
volume - volumi 413
Totale 87.690
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021314 0 0 0 0 0 0 0 0 0 0 70 244
2021/2022819 59 59 111 51 45 42 28 52 57 88 132 95
2022/20231.201 107 110 55 180 101 134 18 78 170 102 74 72
2023/2024977 52 67 129 122 129 130 53 16 35 126 14 104
2024/20251.967 28 32 69 72 256 137 181 170 325 159 253 285
2025/20268.119 1.355 1.209 437 612 498 436 1.429 370 786 830 157 0
Totale 16.870