With the Internet-of-Things revolution, the security assessment against implementation attacks has become a critical concern not only for hardware accelerators but also for embedded CPUs executing cryptographic primitives. Starting from an FPGA implementation of the open-hardware ORPSoC system-on-chip running a software version of the AES, this paper explores two implications of the side-channel information leakage that impact the hardware design of general purpose computing platforms. First, we explore the mapping between the side-channel information leakage and the microarchitectural components that are contributing to it. Second, we discuss the variations in the observability of the side-channel information leakage at post-synthesis and

Analysis and countermeasures to side-channel attacks: a hardware design perspective

davide zoni
2019

Abstract

With the Internet-of-Things revolution, the security assessment against implementation attacks has become a critical concern not only for hardware accelerators but also for embedded CPUs executing cryptographic primitives. Starting from an FPGA implementation of the open-hardware ORPSoC system-on-chip running a software version of the AES, this paper explores two implications of the side-channel information leakage that impact the hardware design of general purpose computing platforms. First, we explore the mapping between the side-channel information leakage and the microarchitectural components that are contributing to it. Second, we discuss the variations in the observability of the side-channel information leakage at post-synthesis and
2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)
978-1-7281-4770-3
978-1-7281-4771-0
Embedded Systems Security, Side Channel Attacks, Hardware Design Flow, Applied Cryptography
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1091953
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