Abstract— Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for current and future multi- cores. In such a scenario power represents a major design obstacle, requiring accurate early-stage estimation for both cores and NoCs. In this perspective, Dynamic Frequency Scaling (DFS) techniques have been proposed as a flexible and scalable way to optimize the power-performance trade-off. However, there is a lack of tools that allow for an early-stage evaluation of different DFS solutions as well as asynchronous NoC. This work proposes a new cycle-accurate simulation framework supporting asynchronous NoC design, allowing also to assess heterogeneous and dynamic frequency schemes for NoC routers.

A cycle accurate simulation framework for asynchronous NoC design

TERRANEO, FEDERICO;ZONI, DAVIDE;FORNACIARI, WILLIAM
2013

Abstract

Abstract— Network-on-Chip (NoC) represents a flexible and scalable interconnection candidate for current and future multi- cores. In such a scenario power represents a major design obstacle, requiring accurate early-stage estimation for both cores and NoCs. In this perspective, Dynamic Frequency Scaling (DFS) techniques have been proposed as a flexible and scalable way to optimize the power-performance trade-off. However, there is a lack of tools that allow for an early-stage evaluation of different DFS solutions as well as asynchronous NoC. This work proposes a new cycle-accurate simulation framework supporting asynchronous NoC design, allowing also to assess heterogeneous and dynamic frequency schemes for NoC routers.
System on Chip (SoC), 2013 International Symposium on
9781479911912
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/760659
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