This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the BlackOut architecture is a fine-grained power-gating methodology targeting individual router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the system performance; (b) the NoCAlert framework is a comprehensive on-line and real-time fault-detection and localization mechanism. Based on the concept of invariance checking, NoCAlert employs a group of lightweight micro-checker modules that collectively implement real-tim5e hardware assertions. Overall, the two solutions demonstrate the potential for ultrafast and low-cost monitor-and-knob mechanisms that can be applied to the NoC of multi-/many-core chips.

Monitor and Knob Techniques in Network-on-Chip Architectures

Davide Zoni;CANIDIO, ANDREA;William Fornaciari
2019

Abstract

This chapter proposes and analyzes two autonomous, hardware-based monitor/knob solutions for Network-on-Chip (NoC) architectures, which operate at the micro-architectural level. The two proposed techniques tackle power and reliability issues pertaining to the NoC: (a) the BlackOut architecture is a fine-grained power-gating methodology targeting individual router buffers. Its goal is to minimize leakage power consumption, without adversely impacting the system performance; (b) the NoCAlert framework is a comprehensive on-line and real-time fault-detection and localization mechanism. Based on the concept of invariance checking, NoCAlert employs a group of lightweight micro-checker modules that collectively implement real-tim5e hardware assertions. Overall, the two solutions demonstrate the potential for ultrafast and low-cost monitor-and-knob mechanisms that can be applied to the NoC of multi-/many-core chips.
Harnessing Performance Variability in Embedded and High-performance Many/Multi-core Platforms
978-3-319-91961-4
978-3-319-91962-1
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1066942
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