| Nome |
# |
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An FPU design template to optimize the accuracy-efficiency-area trade-off, file e0c31c10-6edf-4599-e053-1705fe0aef77
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606
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Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators, file e0c31c09-1666-4599-e053-1705fe0aef77
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484
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A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations, file e0c31c09-1e7b-4599-e053-1705fe0aef77
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446
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Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials, file e0c31c0f-9ddc-4599-e053-1705fe0aef77
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360
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Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks, file e0c31c0d-8f49-4599-e053-1705fe0aef77
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355
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CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs, file e0c31c09-16db-4599-e053-1705fe0aef77
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320
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Integrating Side Channel Security in the FPGA Hardware Design Flow, file e0c31c0f-7496-4599-e053-1705fe0aef77
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307
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Analysis and countermeasures to side-channel attacks: a hardware design perspective, file e0c31c0d-428d-4599-e053-1705fe0aef77
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300
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Cost-effective fixed-point hardware support for RISC-V embedded systems, file cb6c2804-b5e3-4f0b-a72e-cbd9a3e30434
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292
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A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures, file e0c31c09-1725-4599-e053-1705fe0aef77
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256
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Automatic identification and hardware implementation of a resource-constrained power model for embedded systems, file e0c31c10-7268-4599-e053-1705fe0aef77
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240
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All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores, file e0c31c0f-3159-4599-e053-1705fe0aef77
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232
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A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS, file e0c31c09-22f6-4599-e053-1705fe0aef77
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229
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Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography, file e0c31c0f-f876-4599-e053-1705fe0aef77
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222
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VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications, file e0c31c10-01bc-4599-e053-1705fe0aef77
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219
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A sensor-less NBTI mitigation methodology for NoC architectures, file e0c31c09-1720-4599-e053-1705fe0aef77
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173
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Thermal/performance trade-off in network-on-chip architectures, file e0c31c09-16d9-4599-e053-1705fe0aef77
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169
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Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions, file e0c31c0e-cc76-4599-e053-1705fe0aef77
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163
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All-digital energy-constrained controller for general-purpose accelerators and CPUs, file e0c31c0d-4426-4599-e053-1705fe0aef77
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160
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TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale, file e0c31c11-c0e5-4599-e053-1705fe0aef77
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158
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PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring, file e0c31c0c-6382-4599-e053-1705fe0aef77
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145
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A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era, file e0c31c0c-b69f-4599-e053-1705fe0aef77
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140
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BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers, file e0c31c0a-4a9f-4599-e053-1705fe0aef77
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139
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Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations, file e0c31c10-0468-4599-e053-1705fe0aef77
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135
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MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems, file e0c31c11-74e5-4599-e053-1705fe0aef77
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135
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A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture, file e0c31c0d-836c-4599-e053-1705fe0aef77
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130
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On the Effectiveness of True Random Number Generators Implemented on FPGAs, file a002dc0c-77fe-48a4-af0b-d61633d0c086
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105
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On the use of hardware accelerators in QC-MDPC code-based cryptography, file f57d1e69-e447-4c14-9c0f-bfdbecc27f8f
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102
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DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks, file e0c31c0c-1319-4599-e053-1705fe0aef77
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92
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CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties, file e0c31c11-0150-4599-e053-1705fe0aef77
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92
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BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers, file e0c31c0f-8563-4599-e053-1705fe0aef77
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90
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Design of side-channel resistant power monitors, file e0c31c11-84a7-4599-e053-1705fe0aef77
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87
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Exploring Manycore Architectures for Next-Generation HPC Systems through the MANGO Approach, file e0c31c0c-0ecb-4599-e053-1705fe0aef77
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79
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A survey on run-time power monitors at the edge, file ea545e34-c372-429b-89df-38cd5d45f79a
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57
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Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems, file 6a528862-2090-4096-9a4b-d517379e3ccf
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52
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RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project, file ceb20d00-33d1-41df-8a37-1870b06ea923
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47
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Analysis and countermeasures to side-channel attacks: a hardware design perspective, file e0c31c0f-9d4f-4599-e053-1705fe0aef77
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45
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Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials, file e0c31c0f-8c3b-4599-e053-1705fe0aef77
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42
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Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments, file 5f7f5105-823f-4276-a21c-5bd837ecb8ee
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33
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Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems, file 4fa2c46e-7d5f-4cd8-808c-277303acd63a
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30
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Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators, file f82b55d4-a7e8-4da6-9ded-81a8c06a53ab
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30
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Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach, file 97f7d888-0346-45b4-bff1-14e539587a28
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28
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An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE, file 65d080be-f622-45d5-b2e4-b27d1bd88a36
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19
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HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs, file e22cff83-f4ef-479d-88cf-39b98de3d0f4
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16
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A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture, file e0c31c0b-d5e4-4599-e053-1705fe0aef77
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7
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Towards fine-grained DVFS in embedded multi-core CPUs, file e0c31c0c-125d-4599-e053-1705fe0aef77
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7
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Design of side-channel resistant power monitors, file e0c31c11-332c-4599-e053-1705fe0aef77
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7
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Cost-effective fixed-point hardware support for RISC-V embedded systems, file e0c31c12-ba73-4599-e053-1705fe0aef77
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6
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CUTBUF: Buffer Management and Router Design for Traffic Mixing in VNET-based NoCs, file e0c31c0f-2212-4599-e053-1705fe0aef77
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5
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CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties, file e0c31c0a-f2ff-4599-e053-1705fe0aef77
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4
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MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems, file e0c31c0b-5706-4599-e053-1705fe0aef77
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4
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All-digital energy-constrained controller for general-purpose accelerators and CPUs, file e0c31c0f-7c25-4599-e053-1705fe0aef77
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3
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An Accurate Simulation Framework for Thermal Explorations and Optimizations, file e0c31c09-1b90-4599-e053-1705fe0aef77
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2
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DENA: A DVFS-Capable Heterogeneous NoC Architecture, file e0c31c0b-ab82-4599-e053-1705fe0aef77
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2
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PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation, file e0c31c0c-0629-4599-e053-1705fe0aef77
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2
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HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation, file e0c31c0c-c97e-4599-e053-1705fe0aef77
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2
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Una piattaforma informatica per prevenire attacchi ai canali laterali, file e0c31c0f-78bb-4599-e053-1705fe0aef77
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2
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A computing platform and method for synchronize the prototype execution and simulation of hardware devices, file e0c31c0f-8c3c-4599-e053-1705fe0aef77
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2
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Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems, file e0c31c12-946a-4599-e053-1705fe0aef77
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2
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On the use of hardware accelerators in QC-MDPC code-based cryptography, file 63c0b3c4-1d41-452b-bee9-b255ed419092
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1
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Towards Energy-Efficient Functional Configuration in WSNs, file e0c31c07-f191-4599-e053-1705fe0aef77
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1
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Sensor-wise methodology to face NBTI stress of NoC buffers, file e0c31c08-0bdd-4599-e053-1705fe0aef77
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1
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PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring, file e0c31c10-d2ec-4599-e053-1705fe0aef77
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1
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Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators, file e0c31c12-c994-4599-e053-1705fe0aef77
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1
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Design of side-channel resistant power monitors, file e0c31c12-ee28-4599-e053-1705fe0aef77
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1
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| Totale |
7.624 |