All-digital energy-constrained controller for general-purpose accelerators and CPUs

Considering the energy-cap problem in batterypowered devices, DVFS and power gating represent the defacto state-of-the-art actuators. However, the limited margin to reduce the operating voltage, the impossibility to massively integrate such actuators on-chip and their actuation latency force a revision of such design methodologies. We present an all-digital architecture and a design methodology to effectively manage the energy-cap problem for CPUs and accelerators. Two quality metrics are put forward to capture the performance loss and the energy budget violations. We employed a vector processor supporting 4 hardware threads as representative usecase. Results show an average performance loss and energy cap violations limited to 2.9% and 3.8%, respectively. Compared to solutions employing the DFS actuator, our all-digital architecture improves the energy-cap violations by 3x with a similar performance loss.