In current multi-core scenario, Networks-on-Chip (NoC) represent a suitable choice to face the increasing communication and performance requirements, however introducing additional design challenges to already complex architectures. In this perspective, there is a need for flexible and configurable virtual platforms for early-stage design exploration. We present the Heterogeneous Architectures and Networks-on-Chip Design and Simulation framework for large-scale high-performance computer simulation, integrating performance, power, thermal and reliability metrics under a unique methodology. Moreover, NoC exploration is possible from a reliability/performance and thermal/performance trade-offs. © 2012 ACM.

HANDS: Heterogeneous Architectures and Networks-on-Chip Design and Simulation

Zoni, Davide;Corbetta, Simone;Fornaciari, William
2012

Abstract

In current multi-core scenario, Networks-on-Chip (NoC) represent a suitable choice to face the increasing communication and performance requirements, however introducing additional design challenges to already complex architectures. In this perspective, there is a need for flexible and configurable virtual platforms for early-stage design exploration. We present the Heterogeneous Architectures and Networks-on-Chip Design and Simulation framework for large-scale high-performance computer simulation, integrating performance, power, thermal and reliability metrics under a unique methodology. Moreover, NoC exploration is possible from a reliability/performance and thermal/performance trade-offs. © 2012 ACM.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPD'12)
9781450312493
multi-core; network-on-chip; reliability; simulation; Engineering (all)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1070317
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