A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture

Side channel attacks are a prominent threat to the security of embedded systems. To perform them, an adversary evaluates the goodness of fit of a set of key-dependent power consumption models to a collection of side channel measurements taken from an actual device, identifying the secret key value as the one yielding the best fitting model. In this work, we analyze for the first time the microarchitectural components of a 32-bit in-order RISC CPU, showing which one of them are accountable for unexpected side channel information leakage. We classify the leakage sources, identifying the data serialization points in the microarchitecture and providing a set of hints which can be fruitfully exploited to generate implementations resistant against side channel attacks, either writing or generating proper assembly code.