On-chip networks (NoCs) promise to become an efficient communication infrastructure for multi-core architectures. However, there is still a need for efficient power-performance methodologies, since the interconnect power-envelope is really slim and cannot be neglected. Indeed, new power-aware design explorations in current and future multicore systems are needed. The possibility to use different router microarchitectural options and different routing algorithms to increase performance, combined with standard power-aware mechanisms, i.e. DVFS and Power Gating techniques, provides a huge design space to be explored. In this perspective, this paper presents a comparative analysis of different NoC routing algorithms combined with Dynamic Frequency Scaling (DFS).

Adaptive routing and dynamic frequency scaling for NoC power-performance optimizations

ZONI, DAVIDE;FORNACIARI, WILLIAM
2013

Abstract

On-chip networks (NoCs) promise to become an efficient communication infrastructure for multi-core architectures. However, there is still a need for efficient power-performance methodologies, since the interconnect power-envelope is really slim and cannot be neglected. Indeed, new power-aware design explorations in current and future multicore systems are needed. The possibility to use different router microarchitectural options and different routing algorithms to increase performance, combined with standard power-aware mechanisms, i.e. DVFS and Power Gating techniques, provides a huge design space to be explored. In this perspective, this paper presents a comparative analysis of different NoC routing algorithms combined with Dynamic Frequency Scaling (DFS).
PATMOS/VARI’2013 IEEE International Workshop
9781479911707
Network on chip, multi core, power optimization, Dynamic Frequency Scaling
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/760685
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