The power consumption is a key metric to design computing platforms. In particular, the variety and complexity of current applications fueled an increasing number of run-time power-aware optimization solutions to dynamically trade the computational power for the power consumption. In this scenario, the online power monitoring methodologies are the core of any power-aware optimization, since the incorrect assessment of the run-time power consumption prevents any effective actuation. This work proposes PowerTap, an all-digital power modeling methodology for designing online power monitoring solutions. In contrast with state-of-the-art solutions, PowerTap adds domain-specific constraints to the data-driven power modeling problem. PowerTap identifies the power model iteratively to balance the accuracy error of the power estimates and the complexity of the final monitoring infrastructure. As a representative use-case, we employed a complex hardware multi-threaded SIMD processor, also considering different operating clock frequencies. The RTL implementation of the identified power model targeting an Xilinx Artix 7 XC7A200T FPGA highlights an accuracy error within 1.79% with an area overhead of 9.95% (LUT) and 3.87% (flip flops) and an average power overhead of 12.17 mW regardless of the operating conditions, i.e., number of software threads and operating frequency.
|Titolo:||PowerTap: All-digital Power Meter Modeling for Run-time Power Monitoring|
|Data di pubblicazione:||2018|
|Appare nelle tipologie:||01.1 Articolo in Rivista|
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