RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 12.614
EU - Europa 6.586
AS - Asia 3.891
SA - Sud America 1.033
AF - Africa 129
Continente sconosciuto - Info sul continente non disponibili 10
OC - Oceania 8
Totale 24.271
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Nazione #
US - Stati Uniti d'America 12.379
RU - Federazione Russa 2.661
SG - Singapore 1.787
IT - Italia 1.301
CN - Cina 1.009
BR - Brasile 911
DE - Germania 432
VN - Vietnam 411
UA - Ucraina 399
SE - Svezia 285
GB - Regno Unito 269
FI - Finlandia 259
AT - Austria 213
CA - Canada 179
ES - Italia 152
IE - Irlanda 144
NL - Olanda 134
FR - Francia 111
HK - Hong Kong 99
KR - Corea 94
PL - Polonia 81
JO - Giordania 78
ID - Indonesia 76
IN - India 65
BD - Bangladesh 50
AR - Argentina 38
CH - Svizzera 35
JP - Giappone 33
MA - Marocco 33
TR - Turchia 32
BE - Belgio 28
MX - Messico 25
ZA - Sudafrica 25
IQ - Iraq 24
CO - Colombia 23
CI - Costa d'Avorio 21
EC - Ecuador 18
UZ - Uzbekistan 18
TW - Taiwan 15
CZ - Repubblica Ceca 14
VE - Venezuela 14
PH - Filippine 13
SA - Arabia Saudita 13
PK - Pakistan 12
GR - Grecia 10
KE - Kenya 10
AE - Emirati Arabi Uniti 9
IL - Israele 8
IR - Iran 8
PE - Perù 8
TN - Tunisia 8
BG - Bulgaria 7
BJ - Benin 7
EU - Europa 7
PY - Paraguay 7
RO - Romania 7
CL - Cile 6
EG - Egitto 6
JM - Giamaica 6
LB - Libano 6
NP - Nepal 6
PT - Portogallo 6
UY - Uruguay 6
KZ - Kazakistan 5
NZ - Nuova Zelanda 5
BY - Bielorussia 4
DK - Danimarca 4
DO - Repubblica Dominicana 4
LT - Lituania 4
MU - Mauritius 4
NO - Norvegia 4
PA - Panama 4
AL - Albania 3
AU - Australia 3
AZ - Azerbaigian 3
CR - Costa Rica 3
DZ - Algeria 3
HU - Ungheria 3
KG - Kirghizistan 3
LU - Lussemburgo 3
SK - Slovacchia (Repubblica Slovacca) 3
SN - Senegal 3
TT - Trinidad e Tobago 3
BB - Barbados 2
BH - Bahrain 2
BO - Bolivia 2
BS - Bahamas 2
EE - Estonia 2
ET - Etiopia 2
HN - Honduras 2
LI - Liechtenstein 2
LK - Sri Lanka 2
LV - Lettonia 2
MY - Malesia 2
NI - Nicaragua 2
OM - Oman 2
RS - Serbia 2
XK - ???statistics.table.value.countryCode.XK??? 2
AF - Afghanistan, Repubblica islamica di 1
AM - Armenia 1
Totale 24.254
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Città #
Ashburn 1.569
Fairfield 1.568
Woodbridge 1.071
Chandler 874
Houston 858
Singapore 817
Seattle 651
Wilmington 650
Ann Arbor 621
Cambridge 521
Milan 492
Santa Clara 441
Moscow 391
Hefei 266
Beijing 247
Jacksonville 241
Boardman 221
Dearborn 209
Vienna 198
Council Bluffs 180
Dublin 144
Dong Ket 141
Lawrence 140
Medford 134
Ottawa 133
Málaga 124
The Dalles 124
Los Angeles 117
San Diego 93
London 85
Helsinki 84
Hong Kong 84
Amman 78
São Paulo 74
Warsaw 73
Buffalo 70
Seoul 67
New York 62
Des Moines 61
Jakarta 60
Dallas 58
Ho Chi Minh City 56
Amsterdam 55
Redmond 51
Frankfurt am Main 43
Chicago 41
Phoenix 38
Kent 36
Hanoi 32
Boydton 31
Redwood City 31
Rio de Janeiro 30
Columbus 29
Shanghai 29
Brussels 27
Rome 27
Washington 27
Casablanca 26
Turku 25
Bern 22
Abidjan 21
Nuremberg 20
Miami 19
Modena 19
Norwalk 18
Seongnam 18
Belo Horizonte 17
Brasília 17
Mountain View 17
Tashkent 17
Düsseldorf 16
Sant'Antimo 16
Verona 16
Ankara 15
Campinas 15
Princeton 15
San Francisco 15
Tokyo 15
Auburn Hills 14
Redondo Beach 14
Montreal 13
Munich 13
Stockholm 13
Tianjin 13
Atlanta 12
Bologna 12
Johannesburg 12
Richland 12
Manaus 11
Oristano 11
Brooklyn 10
Dhaka 10
Lappeenranta 10
Nairobi 10
Newark 10
Padova 10
Quattro Castella 10
Boston 9
Castiglione Chiavarese 9
Chennai 9
Totale 15.301
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 343
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 302
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications 293
The HERMES-technologic and scientific pathfinder 276
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 273
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 259
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems 229
An Evolutionary Approach to Area-Time Optimization of FPGA designs 229
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 225
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 223
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 213
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 208
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 205
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 199
A dynamically scheduled architecture for the synthesis of graph methods 195
A multiprocessor self-reconfigurable jpeg2000 encoder 195
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 195
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 195
Real-time considerations for rugged embedded systems 189
Enabling the high level synthesis of data analytics accelerators 188
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 187
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 185
An Approach to Functional Testing of VLIW Architectures 184
A design methodology to implement memory accesses in High-Level Synthesis 183
High level synthesis of RDF queries for graph analytics 181
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 180
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 179
Automatic parallelization of sequential specifications for symmetric MPSoCs 179
Lightweight DMA management mechanisms for multiprocessors on FPGA 178
Efficient synthesis of graph methods: a dynamically scheduled architecture 177
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 174
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 174
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 173
A Framework for the Functional Verification of SystemC Models 171
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 170
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 169
High-level synthesis of memory bound and irregular parallel applications with Bambu 169
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 169
Scheduling independent liveness analysis for register binding in high level synthesis 168
A dual-priority real-time multiprocessor system on FPGA for automotive applications 167
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 166
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 166
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 164
Fine grain analysis of simulators accuracy for calibrating performance models 164
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 164
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 163
MLIR Loop Optimizations for High-Level Synthesis: a Case Study 162
Considerations on the use of custom accelerators for big data analytics 162
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics 162
An Interrupt Controller for FPGA-based Multiprocessors 162
A Caronte-oriented approach to a network-based educational infrastructure 159
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 159
Extensions of the hArtes Tool Chain 156
Software defined architectures for data analytics 155
Applications Acceleration through Adaptive Hardware Components 154
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 154
Exploiting Outer Loops Vectorization in High Level Synthesis 153
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 152
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 151
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows 151
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 150
Modeling pipelined application with Synchronous Data Flow graphs 149
Functional Test Generation for Behaviorally Sequential Models 148
Higher-Level Synthesis: experimenting with MLIR polyhedral representations for accelerator design 147
An Efficient Heuristic Approach to Solve the Unate Covering Problem 147
Self Reconfigurable Implementation of the JPEG Encoder 146
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem 145
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 145
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators 143
Function Proxies for Improved Resource Sharing in High Level Synthesis 143
Trace-based automated logical debugging for high-level synthesis generated circuits 143
A systemC based framework for the early evaluation of communication architectures 142
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 142
Inter-procedural resource sharing in High Level Synthesis through function proxies 141
System Level Hardware--Software Design Exploration with XCS 141
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 139
Application of a testing framework to VHDL descriptions at different abstraction levels 138
The hArtes Tool Chain 137
An automated flow for the High Level Synthesis of coarse grained parallel applications 137
In Car Audio 136
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 136
An Application of Genetic Algorithms and BDDs to Functional Testing 135
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators 135
hArtes design flow for heterogeneous platforms 134
Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications 132
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems 131
Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis 130
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms 130
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 130
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 129
Synthesis of complex control structures from behavioral SystemC models 128
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 127
Semiconcurrent error detection in data paths 127
High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators 126
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach 126
System-level metrics for hardware/software architectural mapping 126
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms 125
Code transformations based on speculative SDC scheduling 125
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 124
An Efficient Heuristic Approach to Solve the Unate Covering Problem 123
Totale 16.768
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Categoria #
all - tutte 73.612
article - articoli 13.306
book - libri 0
conference - conferenze 56.562
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.744
Totale 147.224
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.212 0 0 0 0 0 81 136 219 135 173 145 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/20241.093 70 173 108 121 68 111 41 143 43 80 20 115
2024/20253.904 34 57 129 86 524 309 227 314 579 266 725 654
2025/20266.640 2.166 1.968 689 943 653 221 0 0 0 0 0 0
Totale 24.586