RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 11.054
EU - Europa 3.464
AS - Asia 1.633
SA - Sud America 477
AF - Africa 36
Continente sconosciuto - Info sul continente non disponibili 7
OC - Oceania 6
Totale 16.677
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Nazione #
US - Stati Uniti d'America 10.887
IT - Italia 1.135
SG - Singapore 841
BR - Brasile 440
DE - Germania 398
UA - Ucraina 393
SE - Svezia 275
VN - Vietnam 261
FI - Finlandia 229
AT - Austria 204
CN - Cina 196
GB - Regno Unito 169
CA - Canada 150
ES - Italia 140
IE - Irlanda 138
FR - Francia 92
JO - Giordania 77
NL - Olanda 65
PL - Polonia 65
ID - Indonesia 58
CH - Svizzera 34
RU - Federazione Russa 33
HK - Hong Kong 32
BE - Belgio 28
KR - Corea 27
IN - India 26
JP - Giappone 17
CZ - Repubblica Ceca 13
TR - Turchia 13
AR - Argentina 12
CI - Costa d'Avorio 11
PH - Filippine 11
BD - Bangladesh 10
CO - Colombia 9
TW - Taiwan 9
GR - Grecia 8
IQ - Iraq 8
MX - Messico 8
BG - Bulgaria 7
BJ - Benin 7
EU - Europa 7
IR - Iran 7
IL - Israele 6
MA - Marocco 6
PT - Portogallo 6
RO - Romania 6
UZ - Uzbekistan 6
AE - Emirati Arabi Uniti 4
CL - Cile 4
EC - Ecuador 4
MU - Mauritius 4
PK - Pakistan 4
AU - Australia 3
AZ - Azerbaigian 3
BY - Bielorussia 3
DK - Danimarca 3
KG - Kirghizistan 3
LU - Lussemburgo 3
NO - Norvegia 3
NZ - Nuova Zelanda 3
SK - Slovacchia (Repubblica Slovacca) 3
TN - Tunisia 3
VE - Venezuela 3
AL - Albania 2
CR - Costa Rica 2
DO - Repubblica Dominicana 2
EE - Estonia 2
JM - Giamaica 2
KE - Kenya 2
KZ - Kazakistan 2
LI - Liechtenstein 2
LK - Sri Lanka 2
NP - Nepal 2
PA - Panama 2
PE - Perù 2
SA - Arabia Saudita 2
UY - Uruguay 2
AF - Afghanistan, Repubblica islamica di 1
AM - Armenia 1
BH - Bahrain 1
BO - Bolivia 1
CY - Cipro 1
DZ - Algeria 1
HR - Croazia 1
HU - Ungheria 1
LV - Lettonia 1
MK - Macedonia 1
MY - Malesia 1
NI - Nicaragua 1
OM - Oman 1
RS - Serbia 1
SN - Senegal 1
ZA - Sudafrica 1
Totale 16.677
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Città #
Fairfield 1.568
Woodbridge 1.071
Chandler 873
Houston 849
Ashburn 836
Wilmington 650
Seattle 648
Ann Arbor 621
Cambridge 521
Santa Clara 426
Milan 364
Singapore 362
Jacksonville 240
Boardman 213
Dearborn 209
Vienna 195
Council Bluffs 178
Dong Ket 141
Lawrence 140
Dublin 138
Medford 134
Ottawa 133
Málaga 124
The Dalles 117
San Diego 93
Helsinki 83
Amman 77
Beijing 77
Des Moines 61
Jakarta 58
Warsaw 58
Redmond 51
New York 46
Amsterdam 34
São Paulo 33
Redwood City 31
Boydton 30
Phoenix 29
Brussels 27
Washington 26
Frankfurt am Main 24
Rome 23
Bern 22
Columbus 21
Hong Kong 20
Shanghai 20
London 19
Modena 19
Los Angeles 18
Norwalk 18
Seongnam 18
Mountain View 17
Rio de Janeiro 17
Düsseldorf 16
Miami 16
Nuremberg 16
Sant'Antimo 16
Verona 16
Princeton 15
Auburn Hills 14
Chicago 14
Richland 12
Abidjan 11
Belo Horizonte 11
Bologna 11
Oristano 11
Padova 10
Brasília 9
Campinas 9
Castiglione Chiavarese 9
Falkenstein 9
Madrid 8
Meppel 8
Parma 8
Bergamo 7
Cotonou 7
Falls Church 7
Florence 7
Hefei 7
Istanbul 7
Manila 7
Naples 7
Newark 7
Guangzhou 6
Harbor City 6
Indiana 6
Prague 6
Recife 6
Turin 6
Collecchio 5
Crema 5
Lappeenranta 5
Manaus 5
Ostrava 5
Ribeirão Preto 5
Salvador 5
San Francisco 5
Tashkent 5
Torino 5
Americana 4
Totale 12.223
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 258
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 198
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 190
The HERMES-technologic and scientific pathfinder 189
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 178
An Evolutionary Approach to Area-Time Optimization of FPGA designs 173
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 173
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 166
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 164
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 151
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 151
A multiprocessor self-reconfigurable jpeg2000 encoder 149
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 149
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 148
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications 147
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 147
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 145
Real-time considerations for rugged embedded systems 144
An Approach to Functional Testing of VLIW Architectures 142
A dynamically scheduled architecture for the synthesis of graph methods 141
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 139
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 138
Enabling the high level synthesis of data analytics accelerators 136
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 135
Lightweight DMA management mechanisms for multiprocessors on FPGA 134
High level synthesis of RDF queries for graph analytics 134
Extensions of the hArtes Tool Chain 134
High-level synthesis of memory bound and irregular parallel applications with Bambu 132
A design methodology to implement memory accesses in High-Level Synthesis 131
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 127
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 126
Self Reconfigurable Implementation of the JPEG Encoder 125
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 125
Automatic parallelization of sequential specifications for symmetric MPSoCs 125
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 124
Functional Test Generation for Behaviorally Sequential Models 124
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 123
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 121
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 120
Application of a testing framework to VHDL descriptions at different abstraction levels 120
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 120
Fine grain analysis of simulators accuracy for calibrating performance models 119
Scheduling independent liveness analysis for register binding in high level synthesis 119
System Level Hardware--Software Design Exploration with XCS 119
A dual-priority real-time multiprocessor system on FPGA for automotive applications 119
Modeling pipelined application with Synchronous Data Flow graphs 118
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 118
An Interrupt Controller for FPGA-based Multiprocessors 118
Applications Acceleration through Adaptive Hardware Components 117
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 117
An Efficient Heuristic Approach to Solve the Unate Covering Problem 115
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 115
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 115
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 114
A Framework for the Functional Verification of SystemC Models 111
Software defined architectures for data analytics 111
Efficient synthesis of graph methods: a dynamically scheduled architecture 110
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 109
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 109
hArtes design flow for heterogeneous platforms 108
The hArtes Tool Chain 107
Exploiting Outer Loops Vectorization in High Level Synthesis 107
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 106
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 105
Trace-based automated logical debugging for high-level synthesis generated circuits 104
Considerations on the use of custom accelerators for big data analytics 104
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 102
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 101
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 101
An Efficient Heuristic Approach to Solve the Unate Covering Problem 99
An Application of Genetic Algorithms and BDDs to Functional Testing 99
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 99
An automated flow for the High Level Synthesis of coarse grained parallel applications 99
Function Proxies for Improved Resource Sharing in High Level Synthesis 99
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows 98
Inter-procedural resource sharing in High Level Synthesis through function proxies 97
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 97
System-level metrics for hardware/software architectural mapping 96
In Car Audio 96
Automatic Test Pattern Generation with BOA 96
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 96
Semiconcurrent error detection in data paths 96
Property verification in the design of telecom applications 95
Synthesis of complex control structures from behavioral SystemC models 94
BIST Architectures Selection Based on Behavioral Testing 94
Test generation for networks of interacting FSMs using symbolic techniques 94
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms 93
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 92
Functional verification for SystemC descriptions using constraint solving 92
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms 91
Reduction of fault detection costs through a BDD formalism 91
Performance Estimation of Task Graphs Based on Path Profiling 91
A Caronte-oriented approach to a network-based educational infrastructure 90
Instructions activating conditions for hardware-based auto-scheduling 90
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems 90
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow 90
Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications 90
Error simulation based on the SystemC design description language 89
A systemC based framework for the early evaluation of communication architectures 88
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 88
Totale 12.023
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Categoria #
all - tutte 56.597
article - articoli 10.372
book - libri 0
conference - conferenze 43.238
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.987
Totale 113.194
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/2020369 0 0 0 0 0 0 0 0 0 0 258 111
2020/20211.930 177 106 140 153 142 81 136 219 135 173 145 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/20241.093 70 173 108 121 68 111 41 143 43 80 20 115
2024/20252.943 34 57 129 86 524 309 227 314 579 266 418 0
Totale 16.985