RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 12.984
EU - Europa 6.631
AS - Asia 4.238
SA - Sud America 1.043
AF - Africa 166
Continente sconosciuto - Info sul continente non disponibili 10
OC - Oceania 8
Totale 25.080
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Nazione #
US - Stati Uniti d'America 12.728
RU - Federazione Russa 2.661
SG - Singapore 1.994
IT - Italia 1.306
CN - Cina 1.120
BR - Brasile 918
DE - Germania 433
VN - Vietnam 415
UA - Ucraina 399
SE - Svezia 290
GB - Regno Unito 281
FI - Finlandia 259
AT - Austria 214
CA - Canada 192
ES - Italia 154
IE - Irlanda 145
NL - Olanda 138
FR - Francia 112
HK - Hong Kong 104
KR - Corea 95
PL - Polonia 91
JO - Giordania 78
ID - Indonesia 76
IN - India 73
MA - Marocco 65
BD - Bangladesh 51
AR - Argentina 40
JP - Giappone 37
CH - Svizzera 35
TR - Turchia 33
MX - Messico 32
BE - Belgio 28
ZA - Sudafrica 27
IQ - Iraq 24
CO - Colombia 23
CI - Costa d'Avorio 21
EC - Ecuador 18
UZ - Uzbekistan 18
TW - Taiwan 16
VE - Venezuela 15
CZ - Repubblica Ceca 14
PH - Filippine 14
PK - Pakistan 13
SA - Arabia Saudita 13
KE - Kenya 11
GR - Grecia 10
AE - Emirati Arabi Uniti 9
IL - Israele 8
IR - Iran 8
PE - Perù 8
TN - Tunisia 8
BG - Bulgaria 7
BJ - Benin 7
EU - Europa 7
LB - Libano 7
PY - Paraguay 7
RO - Romania 7
CL - Cile 6
EG - Egitto 6
JM - Giamaica 6
LT - Lituania 6
NP - Nepal 6
PT - Portogallo 6
UY - Uruguay 6
KZ - Kazakistan 5
NZ - Nuova Zelanda 5
AL - Albania 4
BY - Bielorussia 4
CR - Costa Rica 4
DK - Danimarca 4
DO - Repubblica Dominicana 4
MU - Mauritius 4
NO - Norvegia 4
PA - Panama 4
AU - Australia 3
AZ - Azerbaigian 3
DZ - Algeria 3
HU - Ungheria 3
KG - Kirghizistan 3
LU - Lussemburgo 3
SK - Slovacchia (Repubblica Slovacca) 3
SN - Senegal 3
TT - Trinidad e Tobago 3
BB - Barbados 2
BH - Bahrain 2
BO - Bolivia 2
BS - Bahamas 2
EE - Estonia 2
ET - Etiopia 2
HN - Honduras 2
LI - Liechtenstein 2
LK - Sri Lanka 2
LV - Lettonia 2
MY - Malesia 2
NI - Nicaragua 2
OM - Oman 2
RS - Serbia 2
XK - ???statistics.table.value.countryCode.XK??? 2
AF - Afghanistan, Repubblica islamica di 1
AM - Armenia 1
Totale 25.060
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Città #
Ashburn 1.626
Fairfield 1.568
Woodbridge 1.071
Singapore 877
Chandler 874
Houston 860
Seattle 651
Wilmington 650
Ann Arbor 621
Cambridge 521
Milan 492
Santa Clara 446
Moscow 391
Hefei 266
Beijing 252
Jacksonville 241
Boardman 221
Dearborn 209
Council Bluffs 208
Vienna 198
San Jose 150
Dublin 145
Dong Ket 141
Lawrence 140
Medford 134
Ottawa 133
Los Angeles 125
Málaga 124
The Dalles 124
San Diego 93
London 90
Hong Kong 89
New York 85
Helsinki 84
Warsaw 82
Amman 78
São Paulo 77
Buffalo 70
Seoul 67
Des Moines 61
Dallas 60
Jakarta 60
Ho Chi Minh City 57
Amsterdam 56
Redmond 51
Frankfurt am Main 43
Chicago 42
Phoenix 39
Kent 36
Shanghai 35
Hanoi 34
Kenitra 33
Boydton 31
Redwood City 31
Rio de Janeiro 30
Columbus 29
Rome 28
Brussels 27
Orem 27
Washington 27
Casablanca 26
Turku 25
Montreal 23
Bern 22
Abidjan 21
Nuremberg 21
Miami 20
Modena 19
Tokyo 19
Norwalk 18
Seongnam 18
Stockholm 18
Belo Horizonte 17
Brasília 17
Mountain View 17
Tashkent 17
Ankara 16
Düsseldorf 16
Sant'Antimo 16
Tianjin 16
Verona 16
Campinas 15
Princeton 15
San Francisco 15
Atlanta 14
Auburn Hills 14
Chennai 14
Johannesburg 14
Redondo Beach 14
Guangzhou 13
Munich 13
Bologna 12
Brooklyn 12
Denver 12
Richland 12
Boston 11
Manaus 11
Nairobi 11
Oristano 11
Changsha 10
Totale 15.752
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 357
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 312
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications 301
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 281
The HERMES-technologic and scientific pathfinder 281
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 268
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems 236
An Evolutionary Approach to Area-Time Optimization of FPGA designs 233
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 230
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 229
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 221
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 212
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 212
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 204
A dynamically scheduled architecture for the synthesis of graph methods 200
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 200
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 200
A multiprocessor self-reconfigurable jpeg2000 encoder 199
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 196
Real-time considerations for rugged embedded systems 195
Enabling the high level synthesis of data analytics accelerators 192
A design methodology to implement memory accesses in High-Level Synthesis 190
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 189
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 188
High level synthesis of RDF queries for graph analytics 187
An Approach to Functional Testing of VLIW Architectures 186
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 185
Automatic parallelization of sequential specifications for symmetric MPSoCs 185
Efficient synthesis of graph methods: a dynamically scheduled architecture 182
Lightweight DMA management mechanisms for multiprocessors on FPGA 180
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 180
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 178
A Framework for the Functional Verification of SystemC Models 178
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 177
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 177
A dual-priority real-time multiprocessor system on FPGA for automotive applications 175
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 174
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 173
Scheduling independent liveness analysis for register binding in high level synthesis 173
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 172
High-level synthesis of memory bound and irregular parallel applications with Bambu 172
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 172
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 171
Fine grain analysis of simulators accuracy for calibrating performance models 171
A Caronte-oriented approach to a network-based educational infrastructure 168
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 168
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 168
MLIR Loop Optimizations for High-Level Synthesis: a Case Study 167
An Interrupt Controller for FPGA-based Multiprocessors 167
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics 166
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 166
Considerations on the use of custom accelerators for big data analytics 165
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 161
Extensions of the hArtes Tool Chain 161
Software defined architectures for data analytics 159
Applications Acceleration through Adaptive Hardware Components 158
Modeling pipelined application with Synchronous Data Flow graphs 156
Exploiting Outer Loops Vectorization in High Level Synthesis 156
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators 155
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 155
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 155
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 155
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows 154
Higher-Level Synthesis: experimenting with MLIR polyhedral representations for accelerator design 152
An Efficient Heuristic Approach to Solve the Unate Covering Problem 151
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 151
Self Reconfigurable Implementation of the JPEG Encoder 150
Functional Test Generation for Behaviorally Sequential Models 150
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem 149
Trace-based automated logical debugging for high-level synthesis generated circuits 148
A systemC based framework for the early evaluation of communication architectures 147
Function Proxies for Improved Resource Sharing in High Level Synthesis 146
Inter-procedural resource sharing in High Level Synthesis through function proxies 146
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 145
System Level Hardware--Software Design Exploration with XCS 145
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 144
The hArtes Tool Chain 143
In Car Audio 142
Application of a testing framework to VHDL descriptions at different abstraction levels 142
An Application of Genetic Algorithms and BDDs to Functional Testing 141
An automated flow for the High Level Synthesis of coarse grained parallel applications 140
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 140
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators 139
hArtes design flow for heterogeneous platforms 137
Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications 137
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach 136
Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis 134
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 134
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems 134
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 133
High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators 132
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms 132
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 131
Synthesis of complex control structures from behavioral SystemC models 131
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms 131
System-level metrics for hardware/software architectural mapping 130
Performance Estimation of Task Graphs Based on Path Profiling 130
Code transformations based on speculative SDC scheduling 129
Semiconcurrent error detection in data paths 129
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 127
Totale 17.292
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Categoria #
all - tutte 75.239
article - articoli 13.620
book - libri 0
conference - conferenze 57.799
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 3.820
Totale 150.478
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/20211.131 0 0 0 0 0 0 136 219 135 173 145 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/20241.093 70 173 108 121 68 111 41 143 43 80 20 115
2024/20253.904 34 57 129 86 524 309 227 314 579 266 725 654
2025/20267.449 2.166 1.968 689 943 653 778 252 0 0 0 0 0
Totale 25.395