RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 15.040
EU - Europa 7.579
AS - Asia 6.103
SA - Sud America 1.121
AF - Africa 191
Continente sconosciuto - Info sul continente non disponibili 10
OC - Oceania 8
Totale 30.052
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Nazione #
US - Stati Uniti d'America 14.746
RU - Federazione Russa 2.662
SG - Singapore 2.269
IT - Italia 1.913
CN - Cina 1.550
BR - Brasile 971
VN - Vietnam 871
DE - Germania 469
UA - Ucraina 405
KR - Corea 349
GB - Regno Unito 311
FR - Francia 299
FI - Finlandia 293
SE - Svezia 291
JP - Giappone 217
HK - Hong Kong 216
AT - Austria 215
CA - Canada 212
ES - Italia 157
IE - Irlanda 147
NL - Olanda 147
PL - Polonia 102
ID - Indonesia 86
IN - India 86
JO - Giordania 79
BD - Bangladesh 75
MA - Marocco 66
TW - Taiwan 47
AR - Argentina 43
MX - Messico 40
CH - Svizzera 38
IQ - Iraq 37
TR - Turchia 36
ZA - Sudafrica 33
BE - Belgio 30
PH - Filippine 27
CO - Colombia 25
UZ - Uzbekistan 22
CI - Costa d'Avorio 21
EC - Ecuador 21
PK - Pakistan 19
VE - Venezuela 18
SA - Arabia Saudita 17
CL - Cile 15
KE - Kenya 15
CZ - Repubblica Ceca 14
AE - Emirati Arabi Uniti 12
TN - Tunisia 12
NP - Nepal 11
PE - Perù 11
GR - Grecia 10
BG - Bulgaria 9
IL - Israele 8
IR - Iran 8
PT - Portogallo 8
PY - Paraguay 8
RO - Romania 8
BJ - Benin 7
EG - Egitto 7
EU - Europa 7
JM - Giamaica 7
LB - Libano 7
LT - Lituania 7
TH - Thailandia 7
AZ - Azerbaigian 6
CR - Costa Rica 6
KZ - Kazakistan 6
TT - Trinidad e Tobago 6
UY - Uruguay 6
AL - Albania 5
DK - Danimarca 5
KG - Kirghizistan 5
MY - Malesia 5
NZ - Nuova Zelanda 5
SN - Senegal 5
BY - Bielorussia 4
DO - Repubblica Dominicana 4
ET - Etiopia 4
HN - Honduras 4
HR - Croazia 4
MU - Mauritius 4
NI - Nicaragua 4
NO - Norvegia 4
OM - Oman 4
PA - Panama 4
RS - Serbia 4
AU - Australia 3
BO - Bolivia 3
CY - Cipro 3
DZ - Algeria 3
HU - Ungheria 3
LK - Sri Lanka 3
LU - Lussemburgo 3
LV - Lettonia 3
PS - Palestinian Territory 3
SK - Slovacchia (Repubblica Slovacca) 3
AM - Armenia 2
AO - Angola 2
BB - Barbados 2
BH - Bahrain 2
Totale 30.018
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Città #
Ashburn 2.052
Fairfield 1.568
Singapore 1.075
Woodbridge 1.071
Milan 1.029
San Jose 1.011
Chandler 874
Houston 860
Seattle 653
Wilmington 650
Ann Arbor 621
Cambridge 521
Santa Clara 462
Moscow 391
The Dalles 330
Seoul 314
Council Bluffs 290
Beijing 275
Hefei 266
Jacksonville 241
Boardman 221
Dearborn 209
Vienna 199
Ho Chi Minh City 196
Tokyo 191
Hong Kong 172
Los Angeles 168
Lauterbourg 161
Hanoi 153
Dublin 147
Dong Ket 141
Lawrence 140
Medford 135
Ottawa 133
Málaga 124
Dallas 118
Helsinki 117
North Charleston 116
New York 99
San Diego 93
Warsaw 93
London 92
São Paulo 84
Amman 79
Buffalo 73
Frankfurt am Main 67
Amsterdam 62
Jakarta 62
Des Moines 61
Redmond 51
Chicago 45
Shanghai 45
Las Vegas 42
Orem 40
Phoenix 40
Bologna 39
Kent 36
Rome 35
Taipei 35
Kenitra 33
Rio de Janeiro 33
Boydton 31
Redwood City 31
Columbus 30
Montreal 29
Washington 29
Da Nang 28
Brussels 27
Haiphong 27
Casablanca 26
Guangzhou 26
Turku 25
Nuremberg 23
Bern 22
Abidjan 21
Atlanta 21
Miami 21
Modena 21
Tashkent 21
Belo Horizonte 19
Johannesburg 18
Norwalk 18
Seongnam 18
Stockholm 18
Tianjin 18
Brasília 17
Chennai 17
Mountain View 17
Ankara 16
Campinas 16
Düsseldorf 16
Hillsboro 16
Sant'Antimo 16
Verona 16
Changsha 15
Nairobi 15
Princeton 15
San Francisco 15
Auburn Hills 14
Denver 14
Totale 19.537
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 513
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 481
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 431
The HERMES-technologic and scientific pathfinder 418
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 376
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications 316
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 300
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 269
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 261
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems 258
An Evolutionary Approach to Area-Time Optimization of FPGA designs 257
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 243
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 239
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 237
Efficient synthesis of graph methods: a dynamically scheduled architecture 230
Enabling the high level synthesis of data analytics accelerators 228
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 225
A Framework for the Functional Verification of SystemC Models 224
A multiprocessor self-reconfigurable jpeg2000 encoder 224
A dynamically scheduled architecture for the synthesis of graph methods 223
High level synthesis of RDF queries for graph analytics 222
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 222
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 221
Real-time considerations for rugged embedded systems 220
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 219
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 218
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 212
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 211
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics 210
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 210
A design methodology to implement memory accesses in High-Level Synthesis 208
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 208
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 208
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 205
MLIR Loop Optimizations for High-Level Synthesis: a Case Study 204
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 204
An Approach to Functional Testing of VLIW Architectures 204
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 203
Automatic parallelization of sequential specifications for symmetric MPSoCs 202
A dual-priority real-time multiprocessor system on FPGA for automotive applications 201
Considerations on the use of custom accelerators for big data analytics 196
Scheduling independent liveness analysis for register binding in high level synthesis 195
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows 195
A Caronte-oriented approach to a network-based educational infrastructure 194
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 194
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 194
Lightweight DMA management mechanisms for multiprocessors on FPGA 193
Fine grain analysis of simulators accuracy for calibrating performance models 193
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 193
High-level synthesis of memory bound and irregular parallel applications with Bambu 193
An Interrupt Controller for FPGA-based Multiprocessors 192
Software defined architectures for data analytics 191
Extensions of the hArtes Tool Chain 191
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 190
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 189
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators 188
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 188
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem 187
Higher-Level Synthesis: experimenting with MLIR polyhedral representations for accelerator design 187
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 187
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 186
Exploiting Outer Loops Vectorization in High Level Synthesis 183
In Car Audio 178
An automated flow for the High Level Synthesis of coarse grained parallel applications 177
Modeling pipelined application with Synchronous Data Flow graphs 176
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 174
Function Proxies for Improved Resource Sharing in High Level Synthesis 174
Inter-procedural resource sharing in High Level Synthesis through function proxies 174
Applications Acceleration through Adaptive Hardware Components 173
Trace-based automated logical debugging for high-level synthesis generated circuits 173
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 172
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach 169
An Efficient Heuristic Approach to Solve the Unate Covering Problem 169
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators 169
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 168
A systemC based framework for the early evaluation of communication architectures 167
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 167
Functional Test Generation for Behaviorally Sequential Models 164
Pre-Scheduling of Affine Loops for HLS Pipelining 163
High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators 163
Self Reconfigurable Implementation of the JPEG Encoder 162
An Application of Genetic Algorithms and BDDs to Functional Testing 159
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 159
Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications 159
Application of a testing framework to VHDL descriptions at different abstraction levels 158
The hArtes Tool Chain 157
System Level Hardware--Software Design Exploration with XCS 156
A DNN-based Background Segmentation Accelerator for FPGA-equipped satellites 155
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems 155
Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis 154
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 154
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 154
Code transformations based on speculative SDC scheduling 154
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 153
hArtes design flow for heterogeneous platforms 153
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 153
High-Level Synthesis Developments in the Context of European Space Technology Research (Invited Talk) 152
An Efficient Heuristic Approach to Solve the Unate Covering Problem 152
System-level metrics for hardware/software architectural mapping 149
A layout-similarity-based approach for detecting phishing pages 148
Totale 20.530
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Categoria #
all - tutte 82.381
article - articoli 14.983
book - libri 0
conference - conferenze 63.276
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 4.122
Totale 164.762
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021641 0 0 0 0 0 0 0 0 0 173 145 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/20241.093 70 173 108 121 68 111 41 143 43 80 20 115
2024/20253.904 34 57 129 86 524 309 227 314 579 266 725 654
2025/202612.422 2.166 1.968 689 943 653 778 2.097 737 1.160 1.231 0 0
Totale 30.368