RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 10.630
EU - Europa 3.194
AS - Asia 970
SA - Sud America 36
AF - Africa 24
Continente sconosciuto - Info sul continente non disponibili 7
OC - Oceania 6
Totale 14.867
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Nazione #
US - Stati Uniti d'America 10.480
IT - Italia 1.070
UA - Ucraina 390
DE - Germania 326
SE - Svezia 272
VN - Vietnam 261
SG - Singapore 247
FI - Finlandia 227
CN - Cina 188
AT - Austria 184
GB - Regno Unito 162
CA - Canada 146
ES - Italia 137
IE - Irlanda 136
JO - Giordania 75
ID - Indonesia 58
PL - Polonia 58
NL - Olanda 55
FR - Francia 43
CH - Svizzera 34
BR - Brasile 30
KR - Corea 27
BE - Belgio 26
IN - India 24
HK - Hong Kong 22
RU - Federazione Russa 22
JP - Giappone 17
CZ - Repubblica Ceca 11
PH - Filippine 11
CI - Costa d'Avorio 10
TR - Turchia 9
TW - Taiwan 9
GR - Grecia 8
BJ - Benin 7
EU - Europa 7
IR - Iran 7
BG - Bulgaria 6
RO - Romania 6
IL - Israele 4
MU - Mauritius 4
PT - Portogallo 4
AR - Argentina 3
AU - Australia 3
LU - Lussemburgo 3
NZ - Nuova Zelanda 3
SK - Slovacchia (Repubblica Slovacca) 3
AE - Emirati Arabi Uniti 2
AZ - Azerbaigian 2
BY - Bielorussia 2
CR - Costa Rica 2
LI - Liechtenstein 2
NO - Norvegia 2
AF - Afghanistan, Repubblica islamica di 1
AL - Albania 1
AM - Armenia 1
BD - Bangladesh 1
CL - Cile 1
DK - Danimarca 1
DO - Repubblica Dominicana 1
DZ - Algeria 1
EC - Ecuador 1
HR - Croazia 1
HU - Ungheria 1
LK - Sri Lanka 1
MA - Marocco 1
MX - Messico 1
MY - Malesia 1
PK - Pakistan 1
RS - Serbia 1
SA - Arabia Saudita 1
TN - Tunisia 1
VE - Venezuela 1
Totale 14.867
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Città #
Fairfield 1.568
Woodbridge 1.071
Chandler 873
Houston 849
Ashburn 828
Wilmington 650
Seattle 647
Ann Arbor 621
Cambridge 521
Santa Clara 425
Milan 337
Jacksonville 240
Boardman 213
Dearborn 209
Vienna 181
Singapore 153
Dong Ket 141
Lawrence 140
Dublin 136
Medford 134
Ottawa 133
Málaga 124
San Diego 93
Helsinki 83
Beijing 76
Amman 75
Des Moines 61
Jakarta 58
Warsaw 56
Redmond 51
New York 46
Amsterdam 32
Redwood City 31
Phoenix 28
Boydton 26
Brussels 26
Washington 26
Bern 22
Columbus 21
Rome 21
Shanghai 20
London 18
Norwalk 18
Seongnam 18
The Dalles 18
Mountain View 17
Miami 16
Sant'Antimo 16
Verona 16
Princeton 15
Auburn Hills 14
Hong Kong 12
Richland 12
Los Angeles 11
Oristano 11
Abidjan 10
Castiglione Chiavarese 9
Chicago 9
Falkenstein 9
Modena 9
Madrid 8
Meppel 8
Padova 8
Bergamo 7
Cotonou 7
Falls Church 7
Florence 7
Hefei 7
Manila 7
Guangzhou 6
Harbor City 6
Indiana 6
Istanbul 6
Naples 6
Turin 6
Collecchio 5
Crema 5
Lappeenranta 5
Ostrava 5
Parma 5
Prague 5
Torino 5
Bologna 4
Brescia 4
Davao City 4
Edinburgh 4
Foggia 4
Grafing 4
Hangzhou 4
Jinan 4
Kilburn 4
Nanjing 4
Portland 4
Seregno 4
Tappahannock 4
Athens 3
Atlanta 3
Berlin 3
Bratislava 3
Brivio 3
Totale 11.508
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 214
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 180
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 178
The HERMES-technologic and scientific pathfinder 175
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 169
An Evolutionary Approach to Area-Time Optimization of FPGA designs 166
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 155
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 153
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 149
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 143
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 140
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 139
A multiprocessor self-reconfigurable jpeg2000 encoder 139
An Approach to Functional Testing of VLIW Architectures 137
Real-time considerations for rugged embedded systems 136
A dynamically scheduled architecture for the synthesis of graph methods 132
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 132
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 132
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 127
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 127
High level synthesis of RDF queries for graph analytics 127
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 127
Extensions of the hArtes Tool Chain 123
Lightweight DMA management mechanisms for multiprocessors on FPGA 122
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 122
High-level synthesis of memory bound and irregular parallel applications with Bambu 122
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 118
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 118
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 116
A design methodology to implement memory accesses in High-Level Synthesis 116
Automatic parallelization of sequential specifications for symmetric MPSoCs 116
Functional Test Generation for Behaviorally Sequential Models 116
Enabling the high level synthesis of data analytics accelerators 115
System Level Hardware--Software Design Exploration with XCS 115
Self Reconfigurable Implementation of the JPEG Encoder 114
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 114
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 112
An Interrupt Controller for FPGA-based Multiprocessors 112
An Efficient Heuristic Approach to Solve the Unate Covering Problem 111
Modeling pipelined application with Synchronous Data Flow graphs 111
Scheduling independent liveness analysis for register binding in high level synthesis 111
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 110
Applications Acceleration through Adaptive Hardware Components 109
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 109
Application of a testing framework to VHDL descriptions at different abstraction levels 108
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 107
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 107
Fine grain analysis of simulators accuracy for calibrating performance models 105
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 105
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 104
A dual-priority real-time multiprocessor system on FPGA for automotive applications 104
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 104
hArtes design flow for heterogeneous platforms 103
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 103
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 102
The hArtes Tool Chain 101
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 101
Efficient synthesis of graph methods: a dynamically scheduled architecture 101
Software defined architectures for data analytics 100
A Framework for the Functional Verification of SystemC Models 99
Exploiting Outer Loops Vectorization in High Level Synthesis 99
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 98
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 97
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 97
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 96
Trace-based automated logical debugging for high-level synthesis generated circuits 96
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 94
An Efficient Heuristic Approach to Solve the Unate Covering Problem 93
An Application of Genetic Algorithms and BDDs to Functional Testing 93
Function Proxies for Improved Resource Sharing in High Level Synthesis 93
Synthesis of complex control structures from behavioral SystemC models 91
Property verification in the design of telecom applications 91
An automated flow for the High Level Synthesis of coarse grained parallel applications 91
Considerations on the use of custom accelerators for big data analytics 91
In Car Audio 90
Test generation for networks of interacting FSMs using symbolic techniques 90
Automatic Test Pattern Generation with BOA 90
System-level metrics for hardware/software architectural mapping 89
Semiconcurrent error detection in data paths 89
Functional verification for SystemC descriptions using constraint solving 87
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms 87
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 87
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms 86
BIST Architectures Selection Based on Behavioral Testing 86
Performance Estimation of Task Graphs Based on Path Profiling 86
Inter-procedural resource sharing in High Level Synthesis through function proxies 85
Reduction of fault detection costs through a BDD formalism 85
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows 85
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 85
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 84
Instructions activating conditions for hardware-based auto-scheduling 84
Error simulation based on the SystemC design description language 84
A systemC based framework for the early evaluation of communication architectures 83
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems 83
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 82
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 82
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow 82
ALADIN: a multilevel testability analyzer for VLSI system design 82
A Caronte-oriented approach to a network-based educational infrastructure 80
BDD-based testability estimation of VHDL designs 80
Totale 10.996
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Categoria #
all - tutte 49.793
article - articoli 9.027
book - libri 0
conference - conferenze 38.067
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.699
Totale 99.586
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2019/20202.175 0 0 0 0 0 441 457 325 404 179 258 111
2020/20211.930 177 106 140 153 142 81 136 219 135 173 145 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/20241.093 70 173 108 121 68 111 41 143 43 80 20 115
2024/20251.126 34 57 129 86 524 296 0 0 0 0 0 0
Totale 15.168