RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
Salva come PNG Salva come JPEG
Continente #
NA - Nord America 15.569
EU - Europa 7.890
AS - Asia 6.136
SA - Sud America 1.124
AF - Africa 191
Continente sconosciuto - Info sul continente non disponibili 11
OC - Oceania 8
Totale 30.929
Salva come PNG Salva come JPEG
Nazione #
US - Stati Uniti d'America 15.256
RU - Federazione Russa 2.662
SG - Singapore 2.285
IT - Italia 2.220
CN - Cina 1.555
BR - Brasile 974
VN - Vietnam 874
DE - Germania 469
UA - Ucraina 405
KR - Corea 349
GB - Regno Unito 313
FR - Francia 300
FI - Finlandia 293
SE - Svezia 291
CA - Canada 224
HK - Hong Kong 217
JP - Giappone 217
AT - Austria 215
ES - Italia 157
NL - Olanda 148
IE - Irlanda 147
PL - Polonia 102
ID - Indonesia 86
IN - India 86
BD - Bangladesh 82
JO - Giordania 79
MA - Marocco 66
TW - Taiwan 47
MX - Messico 44
AR - Argentina 43
CH - Svizzera 38
IQ - Iraq 37
TR - Turchia 36
ZA - Sudafrica 33
BE - Belgio 30
PH - Filippine 27
CO - Colombia 25
UZ - Uzbekistan 22
CI - Costa d'Avorio 21
EC - Ecuador 21
PK - Pakistan 19
VE - Venezuela 18
SA - Arabia Saudita 17
CL - Cile 15
KE - Kenya 15
CZ - Repubblica Ceca 14
AE - Emirati Arabi Uniti 12
NP - Nepal 12
TN - Tunisia 12
PE - Perù 11
GR - Grecia 10
BG - Bulgaria 9
IL - Israele 8
IR - Iran 8
JM - Giamaica 8
PT - Portogallo 8
PY - Paraguay 8
RO - Romania 8
BJ - Benin 7
EG - Egitto 7
EU - Europa 7
LB - Libano 7
LT - Lituania 7
TH - Thailandia 7
TT - Trinidad e Tobago 7
AZ - Azerbaigian 6
CR - Costa Rica 6
KZ - Kazakistan 6
UY - Uruguay 6
AL - Albania 5
DK - Danimarca 5
KG - Kirghizistan 5
MY - Malesia 5
NZ - Nuova Zelanda 5
SN - Senegal 5
BY - Bielorussia 4
DO - Repubblica Dominicana 4
ET - Etiopia 4
HN - Honduras 4
HR - Croazia 4
MU - Mauritius 4
NI - Nicaragua 4
NO - Norvegia 4
OM - Oman 4
PA - Panama 4
RS - Serbia 4
AU - Australia 3
BO - Bolivia 3
CY - Cipro 3
DZ - Algeria 3
HU - Ungheria 3
LK - Sri Lanka 3
LU - Lussemburgo 3
LV - Lettonia 3
PS - Palestinian Territory 3
SK - Slovacchia (Repubblica Slovacca) 3
XK - ???statistics.table.value.countryCode.XK??? 3
AM - Armenia 2
AO - Angola 2
BB - Barbados 2
Totale 30.894
Salva come PNG Salva come JPEG
Città #
Ashburn 2.124
Fairfield 1.568
Milan 1.324
Singapore 1.089
San Jose 1.079
Woodbridge 1.071
Chandler 874
Houston 866
Seattle 653
Wilmington 650
Ann Arbor 621
Cambridge 521
Santa Clara 497
Moscow 391
The Dalles 330
Council Bluffs 317
Seoul 314
Beijing 277
Boardman 268
Hefei 266
Jacksonville 243
Dearborn 209
Vienna 199
Ho Chi Minh City 196
Tokyo 191
Los Angeles 176
Hong Kong 173
Lauterbourg 161
Hanoi 155
Dublin 147
Dong Ket 141
Lawrence 140
Medford 135
Ottawa 133
Málaga 124
Dallas 122
Helsinki 117
North Charleston 116
New York 109
San Diego 93
Warsaw 93
London 92
São Paulo 84
Amman 79
Buffalo 75
Frankfurt am Main 67
Amsterdam 62
Des Moines 62
Jakarta 62
Redmond 51
Chicago 46
Shanghai 46
Las Vegas 42
Phoenix 42
Bologna 40
Orem 40
Kent 36
Rome 36
Taipei 35
Boydton 33
Kenitra 33
Montreal 33
Rio de Janeiro 33
Columbus 31
Redwood City 31
Washington 29
Da Nang 28
Atlanta 27
Brussels 27
Haiphong 27
Casablanca 26
Guangzhou 26
Turku 25
Nuremberg 23
Bern 22
Modena 22
Abidjan 21
Miami 21
Tashkent 21
Belo Horizonte 19
Johannesburg 18
Norwalk 18
Seongnam 18
Stockholm 18
Tianjin 18
Brasília 17
Chennai 17
Mountain View 17
Ankara 16
Campinas 16
Denver 16
Düsseldorf 16
Hillsboro 16
Mexico City 16
San Francisco 16
Sant'Antimo 16
Verona 16
Changsha 15
Nairobi 15
Princeton 15
Totale 20.158
Salva come PNG Salva come JPEG
Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 581
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 546
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 492
The HERMES-technologic and scientific pathfinder 478
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 436
Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications 318
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 303
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 276
A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems 264
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 263
An Evolutionary Approach to Area-Time Optimization of FPGA designs 259
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 246
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 246
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 239
Efficient synthesis of graph methods: a dynamically scheduled architecture 237
Enabling the high level synthesis of data analytics accelerators 236
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 232
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 229
High level synthesis of RDF queries for graph analytics 229
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 227
A Framework for the Functional Verification of SystemC Models 226
A dynamically scheduled architecture for the synthesis of graph methods 226
A multiprocessor self-reconfigurable jpeg2000 encoder 225
Real-time considerations for rugged embedded systems 222
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 221
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 221
Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications 218
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 216
Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics 215
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 213
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 212
A design methodology to implement memory accesses in High-Level Synthesis 211
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 211
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 210
MLIR Loop Optimizations for High-Level Synthesis: a Case Study 207
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 207
An Approach to Functional Testing of VLIW Architectures 206
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 205
Automatic parallelization of sequential specifications for symmetric MPSoCs 203
A dual-priority real-time multiprocessor system on FPGA for automotive applications 202
Considerations on the use of custom accelerators for big data analytics 200
Lightweight DMA management mechanisms for multiprocessors on FPGA 198
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 198
Software defined architectures for data analytics 198
Scheduling independent liveness analysis for register binding in high level synthesis 197
A Caronte-oriented approach to a network-based educational infrastructure 196
Fine grain analysis of simulators accuracy for calibrating performance models 196
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 196
High-level synthesis of memory bound and irregular parallel applications with Bambu 196
A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows 196
Extensions of the hArtes Tool Chain 196
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 196
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 194
An Interrupt Controller for FPGA-based Multiprocessors 192
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem 191
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 191
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 191
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 190
Instructions activating conditions for hardware-based auto-scheduling 190
SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators 189
Higher-Level Synthesis: experimenting with MLIR polyhedral representations for accelerator design 189
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 188
Exploiting Outer Loops Vectorization in High Level Synthesis 184
In Car Audio 183
Inter-procedural resource sharing in High Level Synthesis through function proxies 181
Modeling pipelined application with Synchronous Data Flow graphs 180
An automated flow for the High Level Synthesis of coarse grained parallel applications 180
Trace-based automated logical debugging for high-level synthesis generated circuits 178
Function Proxies for Improved Resource Sharing in High Level Synthesis 177
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 176
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 175
Applications Acceleration through Adaptive Hardware Components 173
A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach 172
An Efficient Heuristic Approach to Solve the Unate Covering Problem 171
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 170
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators 170
Pre-Scheduling of Affine Loops for HLS Pipelining 169
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 169
A systemC based framework for the early evaluation of communication architectures 168
High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators 167
Functional Test Generation for Behaviorally Sequential Models 166
Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications 164
Self Reconfigurable Implementation of the JPEG Encoder 163
The hArtes Tool Chain 163
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 162
Application of a testing framework to VHDL descriptions at different abstraction levels 160
A DNN-based Background Segmentation Accelerator for FPGA-equipped satellites 159
An Application of Genetic Algorithms and BDDs to Functional Testing 159
Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis 157
High-Level Synthesis Developments in the Context of European Space Technology Research (Invited Talk) 157
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 157
Code transformations based on speculative SDC scheduling 157
System Level Hardware--Software Design Exploration with XCS 157
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 156
An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems 156
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 155
hArtes design flow for heterogeneous platforms 155
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 154
Performance Estimation of Task Graphs Based on Path Profiling 154
An Efficient Heuristic Approach to Solve the Unate Covering Problem 152
Totale 21.188
Salva come PNG Salva come JPEG
Categoria #
all - tutte 86.335
article - articoli 15.700
book - libri 0
conference - conferenze 66.356
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 4.279
Totale 172.670
Salva come PNG Salva come JPEG


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2020/2021323 0 0 0 0 0 0 0 0 0 0 0 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/20241.093 70 173 108 121 68 111 41 143 43 80 20 115
2024/20253.904 34 57 129 86 524 309 227 314 579 266 725 654
2025/202613.299 2.166 1.968 689 943 653 778 2.097 737 1.160 1.280 488 340
Totale 31.245