RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

FERRANDI, FABRIZIO
 Distribuzione geografica
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Continente #
NA - Nord America 9.959
EU - Europa 2.972
AS - Asia 605
AF - Africa 13
Continente sconosciuto - Info sul continente non disponibili 7
OC - Oceania 6
SA - Sud America 6
Totale 13.568
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Nazione #
US - Stati Uniti d'America 9.812
IT - Italia 956
UA - Ucraina 389
DE - Germania 302
SE - Svezia 271
VN - Vietnam 261
FI - Finlandia 219
AT - Austria 181
GB - Regno Unito 160
CA - Canada 144
CN - Cina 142
ES - Italia 132
IE - Irlanda 130
JO - Giordania 75
PL - Polonia 57
FR - Francia 42
NL - Olanda 35
KR - Corea 27
BE - Belgio 26
CH - Svizzera 26
IN - India 24
HK - Hong Kong 19
JP - Giappone 15
CI - Costa d'Avorio 9
TW - Taiwan 9
SG - Singapore 8
EU - Europa 7
IR - Iran 7
BG - Bulgaria 6
RO - Romania 6
RU - Federazione Russa 6
CZ - Repubblica Ceca 5
GR - Grecia 5
BR - Brasile 4
IL - Israele 4
MU - Mauritius 4
PH - Filippine 4
TR - Turchia 4
AU - Australia 3
LU - Lussemburgo 3
NZ - Nuova Zelanda 3
SK - Slovacchia (Repubblica Slovacca) 3
AZ - Azerbaigian 2
ID - Indonesia 2
LI - Liechtenstein 2
NO - Norvegia 2
PT - Portogallo 2
AF - Afghanistan, Repubblica islamica di 1
AL - Albania 1
AR - Argentina 1
BY - Bielorussia 1
CL - Cile 1
CR - Costa Rica 1
DK - Danimarca 1
DO - Repubblica Dominicana 1
HR - Croazia 1
HU - Ungheria 1
MX - Messico 1
RS - Serbia 1
SA - Arabia Saudita 1
Totale 13.568
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Città #
Fairfield 1.568
Woodbridge 1.071
Chandler 873
Houston 849
Ashburn 820
Wilmington 650
Seattle 647
Ann Arbor 621
Cambridge 521
Milan 306
Jacksonville 240
Dearborn 209
Vienna 178
Dong Ket 141
Lawrence 140
Medford 134
Ottawa 133
Dublin 130
Málaga 124
San Diego 93
Helsinki 80
Amman 75
Beijing 72
Des Moines 61
Warsaw 56
Redmond 51
New York 36
Boardman 33
Redwood City 31
Phoenix 28
Brussels 26
Washington 26
Boydton 25
Bern 22
Columbus 21
Norwalk 18
Seongnam 18
Mountain View 17
Amsterdam 16
London 16
Miami 16
Sant'Antimo 16
Verona 16
Princeton 15
Shanghai 15
Auburn Hills 14
Rome 13
Richland 12
Oristano 11
Abidjan 9
Castiglione Chiavarese 9
Chicago 9
Hong Kong 9
Los Angeles 8
Meppel 8
Padova 8
Falls Church 7
Florence 7
Hefei 7
Singapore 7
Bergamo 6
Harbor City 6
Indiana 6
Naples 6
Collecchio 5
Crema 5
Guangzhou 5
Santa Clara 5
Torino 5
Bologna 4
Davao City 4
Edinburgh 4
Foggia 4
Grafing 4
Hangzhou 4
Kilburn 4
Nanjing 4
Parma 4
Portland 4
Prague 4
Tappahannock 4
Atlanta 3
Bratislava 3
Brescia 3
Brivio 3
Cassina Valsassina 3
Centrale 3
Cupertino 3
Dronten 3
Duncan 3
Farnborough 3
Iffezheim 3
Jinan 3
Kumar 3
Lonato 3
Madrid 3
Menlo Park 3
Montreal 3
Moscow 3
Nanchang 3
Totale 10.546
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Nome #
A Survey and Evaluation of FPGA High-Level Synthesis Tools 194
A Design Kit for a Fully Working Shared Memory Multiprocessor on FPGA 171
The HERMES-technologic and scientific pathfinder 165
An Evolutionary Approach to Area-Time Optimization of FPGA designs 160
GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam 151
Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops 144
The scientific payload on-board the HERMES-TP and HERMES-SP CubeSat missions 138
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs 137
A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries 134
Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs 132
An Approach to Functional Testing of VLIW Architectures 131
Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis 131
Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis 128
A multiprocessor self-reconfigurable jpeg2000 encoder 127
A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis 126
A Design Methodology for the Automatic Sizing of Standard-Cell Libraries 122
Real-time considerations for rugged embedded systems 122
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers 118
A dynamically scheduled architecture for the synthesis of graph methods 118
Timing techniques applied to distributed modular high-energy astronomy: The HERMES project 118
High level synthesis of RDF queries for graph analytics 117
A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs 115
Lightweight DMA management mechanisms for multiprocessors on FPGA 114
Functional Test Generation for Behaviorally Sequential Models 114
Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA 112
YAPPA: A compiler-based parallelization framework for irregular applications on MPSoCs 112
High-level synthesis of memory bound and irregular parallel applications with Bambu 112
Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems 111
System Level Hardware--Software Design Exploration with XCS 111
An Efficient Heuristic Approach to Solve the Unate Covering Problem 110
A design methodology to implement memory accesses in High-Level Synthesis 109
Self Reconfigurable Implementation of the JPEG Encoder 107
Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems 107
Modeling pipelined application with Synchronous Data Flow graphs 106
Enabling the high level synthesis of data analytics accelerators 106
Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance 106
Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems 105
An Interrupt Controller for FPGA-based Multiprocessors 105
Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP 104
Automatic parallelization of sequential specifications for symmetric MPSoCs 104
Application of a testing framework to VHDL descriptions at different abstraction levels 103
A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture 103
hArtes design flow for heterogeneous platforms 102
Scheduling independent liveness analysis for register binding in high level synthesis 101
hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms 100
Applications Acceleration through Adaptive Hardware Components 100
A dual-priority real-time multiprocessor system on FPGA for automotive applications 99
Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis 99
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems 98
Fine grain analysis of simulators accuracy for calibrating performance models 97
Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications 97
A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells 97
Abstract: Speeding-Up Memory Intensive Applications through Adaptive Hardware Accelerators 95
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 95
Automatic Generation of Heterogeneous SoC Architectures with Secure Communications 95
Exploiting Outer Loops Vectorization in High Level Synthesis 94
A Framework for the Functional Verification of SystemC Models 93
A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis 92
Software defined architectures for data analytics 92
A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency 92
Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems 91
An Efficient Heuristic Approach to Solve the Unate Covering Problem 90
An Application of Genetic Algorithms and BDDs to Functional Testing 90
The hArtes Tool Chain 90
Property verification in the design of telecom applications 89
Test generation for networks of interacting FSMs using symbolic techniques 89
Automatic Test Pattern Generation with BOA 89
Extensions of the hArtes Tool Chain 89
Efficient synthesis of graph methods: a dynamically scheduled architecture 89
Synthesis of complex control structures from behavioral SystemC models 88
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis 88
System-level metrics for hardware/software architectural mapping 87
Dynamic AC-scheduling for hardware cores with unknown and uncertain information 86
Trace-based automated logical debugging for high-level synthesis generated circuits 86
Functional verification for SystemC descriptions using constraint solving 85
BIST Architectures Selection Based on Behavioral Testing 84
Reduction of fault detection costs through a BDD formalism 84
Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System 83
In Car Audio 82
Function Proxies for Improved Resource Sharing in High Level Synthesis 82
Error simulation based on the SystemC design description language 82
An automated flow for the High Level Synthesis of coarse grained parallel applications 81
Considerations on the use of custom accelerators for big data analytics 81
Semiconcurrent error detection in data paths 81
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms 79
A reconfigurable multiprocessor architecture for a reliable face recognition implementation 79
ALADIN: a multilevel testability analyzer for VLSI system design 79
BDD-based testability estimation of VHDL designs 78
VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow 78
Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform 78
Performance Estimation of Task Graphs Based on Path Profiling 78
A systemC based framework for the early evaluation of communication architectures 77
VHDL testability analysis based on fault clustering and implicit fault injection 77
Functional Test Generation 76
Instructions activating conditions for hardware-based auto-scheduling 76
Symbolic optimization of interacting controllers based on redundancy identification and removal 76
Mining Interesting Patterns from Hardware-Software Codesign Data with the Learning Classifier System XCS 76
Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms 75
Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs 75
Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions 75
Totale 10.196
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Categoria #
all - tutte 39.530
article - articoli 7.239
book - libri 0
conference - conferenze 30.135
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 2.156
Totale 79.060
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/20191.317 0 0 0 0 0 0 0 0 0 312 553 452
2019/20203.391 229 197 87 275 428 441 457 325 404 179 258 111
2020/20211.930 177 106 140 153 142 81 136 219 135 173 145 323
2021/20221.693 70 236 158 56 227 75 127 111 80 81 197 275
2022/20232.004 215 151 64 236 211 251 22 162 315 154 124 99
2023/2024915 70 173 108 121 68 111 41 143 43 37 0 0
Totale 13.864