A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique

Testing strategies for complex WSI systems are one of the elements that may prevent the full exploitation of novel technologies, such as multichip modules (MCM's), because of the limited reliability (and quality) of the final product. The application of an efficient test strategy to the circuits of the module is necessary to achieve high-quality, cost-effective devices. The aim of this paper is to introduce a structured approach to the design of testable wafer scale devices. Bare die testability is guaranteed through the application mainly of the partial scan methodology, to provide the most convenient solution in terms of overhead and performance, while module testability is achieved through the application of the boundary scan technique.