The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results. © 1994.
Reduction of fault detection costs through a BDD formalism
FERRANDI, FABRIZIO
1994-01-01
Abstract
The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results. © 1994.File in questo prodotto:
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