The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results. © 1994.

Reduction of fault detection costs through a BDD formalism

FERRANDI, FABRIZIO
1994

Abstract

The paper presents a methodology for an efficient testability analysis of complex VLSI circuit. It is based on controllability/observability evaluation using Binary Decision Diagrams (BDD). Efficiency is improved by intelligent use of intermediate results. © 1994.
Engineering (all)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1006480
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