High performance multimedia applications are typical targets of today embedded systems. These applications, complex both in terms of execution flow and amount of elaborated data, can be well addressed by multiprocessor systems on-chip (MPSoCs). MPSoCs are composed of simple processors and memories tightly interconnected with fast communication channels and customized IP cores for the most demanding functions can be implemented and attached to these systems to enhance performance even more. Reconfigurable devices like FPGA, can act as a target, even programmed at runtime, for the custom IP cores, or as a prototyping platform for the whole system. Image compression like JPEG2000, can benefit very much from this approach and this type of architectures. This paper shows how the most demanding task of the JPEG2000 compression algorithm, the two-dimensional discrete wavelet transform, can be hardware accelerated and implemented in a multiprocessor system-on-chip prototyping platform on field programmable gate array (FPGA), CerberO. Architectures with different number of processors and hardware accelerators, shared among the processors or dedicated, have been implemented. To validate the approach, we show some experimental results on the platform with the hardware and the software implementation of the transformation

Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA

FERRANDI, FABRIZIO;SANTAMBROGIO, MARCO DOMENICO;SCIUTO, DONATELLA;TUMEO, ANTONINO
2006

Abstract

High performance multimedia applications are typical targets of today embedded systems. These applications, complex both in terms of execution flow and amount of elaborated data, can be well addressed by multiprocessor systems on-chip (MPSoCs). MPSoCs are composed of simple processors and memories tightly interconnected with fast communication channels and customized IP cores for the most demanding functions can be implemented and attached to these systems to enhance performance even more. Reconfigurable devices like FPGA, can act as a target, even programmed at runtime, for the custom IP cores, or as a prototyping platform for the whole system. Image compression like JPEG2000, can benefit very much from this approach and this type of architectures. This paper shows how the most demanding task of the JPEG2000 compression algorithm, the two-dimensional discrete wavelet transform, can be hardware accelerated and implemented in a multiprocessor system-on-chip prototyping platform on field programmable gate array (FPGA), CerberO. Architectures with different number of processors and hardware accelerators, shared among the processors or dedicated, have been implemented. To validate the approach, we show some experimental results on the platform with the hardware and the software implementation of the transformation
Embedded Computer Systems: Architectures, Modeling and Simulation, 2006. IC-SAMOS 2006. International Conference on
data compression;discrete wavelet transforms;embedded systems;field programmable gate arrays;image coding;microprocessor chips;system-on-chip;FPGA;discrete wavelet transform;embedded system;field programmable gate array;hardware DWT accelerator;image compression;multimedia application;multiprocessor system-on-chip;Communication channels;Discrete wavelet transforms;Embedded system;Field programmable gate arrays;Hardware;Multimedia systems;Multiprocessing systems;Prototypes;System-on-a-chip;Transform coding
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/249789
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