Application of a testing framework to VHDL descriptions at different abstraction levels

The test problem increasingly affects system design process, related costs and time to market. Requirements from VLSI/WSI manufacturers are for fast and reliable testability tools, with the possibility of their introduction in early phases of design. This paper presents a global tool set architecture for testability analysis and test pattern generation. Three attraction levels am considered iir this design flow, from the behavioral specifications, through RTL descriptions, down to gate level. In all these phases, VHDL is chosen as the referring description language The paper will then present an application scenario, detailing the results achieved by the proposed methodology.