Nome |
# |
A Survey and Evaluation of FPGA High-Level Synthesis Tools, file e0c31c09-de59-4599-e053-1705fe0aef77
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2.885
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Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications, file e0c31c12-1f74-4599-e053-1705fe0aef77
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1.282
|
Inter-procedural resource sharing in High Level Synthesis through function proxies, file e0c31c09-2b49-4599-e053-1705fe0aef77
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877
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Code transformations based on speculative SDC scheduling, file e0c31c09-239e-4599-e053-1705fe0aef77
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654
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Svelto: High-Level Synthesis of Multi-Threaded Accelerators for Graph Analytics, file e0c31c10-c718-4599-e053-1705fe0aef77
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597
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Exploiting Vectorization in High Level Synthesis of Nested Irregular Loops, file e0c31c0a-5873-4599-e053-1705fe0aef77
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575
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High level synthesis of RDF queries for graph analytics, file e0c31c09-21d3-4599-e053-1705fe0aef77
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558
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Computer Assisted Design and Integration of FPGA Accelerators in Aerospace Systems, file e0c31c09-2274-4599-e053-1705fe0aef77
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557
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Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators, file e0c31c12-99f3-4599-e053-1705fe0aef77
|
510
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Using Efficient Path Profiling to Optimize Memory Consumption of On-Chip Debugging for High-Level Synthesis, file e0c31c0b-1ca0-4599-e053-1705fe0aef77
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502
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Efficient synthesis of graph methods: a dynamically scheduled architecture, file e0c31c09-f76e-4599-e053-1705fe0aef77
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470
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Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems, file e0c31c09-2d2b-4599-e053-1705fe0aef77
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444
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Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions, file e0c31c09-1b4f-4599-e053-1705fe0aef77
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441
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Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems, file e0c31c0a-cc24-4599-e053-1705fe0aef77
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417
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A Design Flow Engine for the Support of Customized Dynamic High Level Synthesis Flows, file e0c31c0e-af59-4599-e053-1705fe0aef77
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413
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Performance estimation of embedded software with confidence levels, file e0c31c09-1c20-4599-e053-1705fe0aef77
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406
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Modeling pipelined application with Synchronous Data Flow graphs, file e0c31c09-1c22-4599-e053-1705fe0aef77
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404
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Enabling the high level synthesis of data analytics accelerators, file e0c31c09-dbed-4599-e053-1705fe0aef77
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393
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Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers, file e0c31c09-e741-4599-e053-1705fe0aef77
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380
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Trace-based automated logical debugging for high-level synthesis generated circuits, file e0c31c09-2f45-4599-e053-1705fe0aef77
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371
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Software defined architectures for data analytics, file e0c31c0d-0d29-4599-e053-1705fe0aef77
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365
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Exploiting Outer Loops Vectorization in High Level Synthesis, file e0c31c09-21d6-4599-e053-1705fe0aef77
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355
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Performance Estimation of Task Graphs Based on Path Profiling, file e0c31c09-22b4-4599-e053-1705fe0aef77
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346
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Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis, file e0c31c0c-01d0-4599-e053-1705fe0aef77
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346
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Automated Bug Detection for High-level Synthesis of Multi-threaded Irregular Applications, file e0c31c0f-da29-4599-e053-1705fe0aef77
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332
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Performance modeling of embedded applications with zero architectural knowledge, file e0c31c09-1bc6-4599-e053-1705fe0aef77
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324
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Tensor Optimization for High-Level Synthesis Design Flows, file e0c31c0f-fe87-4599-e053-1705fe0aef77
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319
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A Dynamically Scheduled Architecture for the Synthesis of Graph Database Queries, file e0c31c09-e77b-4599-e053-1705fe0aef77
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307
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Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance, file e0c31c0a-0bf9-4599-e053-1705fe0aef77
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296
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Automatic parallelization of sequential specifications for symmetric MPSoCs, file e0c31c09-1b51-4599-e053-1705fe0aef77
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292
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hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms, file e0c31c09-e1d0-4599-e053-1705fe0aef77
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290
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The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited, file a4cf099a-68ad-4008-8723-42c2bfb025d0
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287
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Modeling Resolution of Resources Contention in Synchronous Data Flow Graphs, file e0c31c09-22b7-4599-e053-1705fe0aef77
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284
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Combining Target-independent Analysis with Dynamic Profiling to Build the Performance Model of a DSP, file e0c31c09-1bc2-4599-e053-1705fe0aef77
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227
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Performance Modeling of Parallel Applications on MPSoCs, file e0c31c09-2381-4599-e053-1705fe0aef77
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227
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Fine grain analysis of simulators accuracy for calibrating performance models, file e0c31c09-1bbf-4599-e053-1705fe0aef77
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224
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Automatic Generation of Heterogeneous SoC Architectures with Secure Communications, file e0c31c0f-d357-4599-e053-1705fe0aef77
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220
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In Car Audio, file e0c31c09-cb16-4599-e053-1705fe0aef77
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183
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End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators, file fac6a9a2-2112-4e07-828f-39353836a0fc
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178
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Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs, file e0c31c09-2e6d-4599-e053-1705fe0aef77
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147
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Hardware acceleration of complex machine learning models through modern high-level synthesis, file b52336f1-04aa-40c7-88da-36987853c7e7
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145
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Tensor Optimization for High-Level Synthesis Design Flows, file e0c31c10-d872-4599-e053-1705fe0aef77
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138
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The hArtes Tool Chain, file e0c31c09-d978-4599-e053-1705fe0aef77
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133
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GrailQuest and HERMES: hunting for gravitational wave electromagnetic counterparts and probing space-time quantum foam, file e0c31c10-cd8e-4599-e053-1705fe0aef77
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122
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Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis, file 314e74e8-f2c5-4d4a-838d-aa0827940d6f
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110
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Partitioning and Mapping for the hArtes European Project, file e0c31c09-238a-4599-e053-1705fe0aef77
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102
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Hardware Acceleration of Complex Machine Learning Models through Modern High-Level Synthesis, file e0c31c12-0a9e-4599-e053-1705fe0aef77
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88
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SODA synthesizer: An open-source, multi-level, modular, extensible compiler from high-level frameworks to silicon, file 528ff192-d39e-44d6-9cb1-f0f81aba2fc2
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67
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Parametric Throughput Oriented Large Integer Multipliers for High Level Synthesis, file e0c31c12-4b5c-4599-e053-1705fe0aef77
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63
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Using High-Level Synthesis to model System Verilog procedural timing controls, file 09bd67ea-45b1-40e3-8b04-b86cf6fd8457
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57
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TrueFloat: A Templatized Arithmetic Library for HLS Floating-Point Operators, file e2629ec7-c0ed-446b-b866-9a4ee537834e
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42
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Hardware Acceleration of Complex Machine Learning Models through Modern High-Level Synthesis, file e0c31c11-e369-4599-e053-1705fe0aef77
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41
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EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms, file e0c31c11-6965-4599-e053-1705fe0aef77
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40
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HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem, file d1194fa8-1dd0-44a2-93ed-ceced2e32094
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32
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Exploration of Synthesis Methods from Simulink Models to FPGA for Aerospace Applications, file f94a6e8b-0228-4547-8e72-2f124c470b0a
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31
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High-Level Synthesis of the OpenMP runtime to improve the generation of parallel accelerators, file 6f2ad79c-0eca-4086-83a7-fc6dcf9f9a47
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24
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MLIR Loop Optimizations for High-Level Synthesis: a Case Study, file c9078e4b-eecd-4183-bcb0-a102986de220
|
16
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hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms, file e0c31c07-e36e-4599-e053-1705fe0aef77
|
5
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hArtes: Holistic Approach to Reconfigurable Real-Time Embedded SystemsReconfigurable Computing, file e0c31c08-0874-4599-e053-1705fe0aef77
|
5
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The HERMES-technologic and scientific pathfinder, file e0c31c11-e1c3-4599-e053-1705fe0aef77
|
4
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In Car Audio, file e0c31c07-f97d-4599-e053-1705fe0aef77
|
3
|
A Survey and Evaluation of FPGA High-Level Synthesis Tools, file e0c31c0a-13cc-4599-e053-1705fe0aef77
|
3
|
Automated Generation of Integrated Digital and Spiking Neuromorphic Machine Learning Accelerators, file e0c31c12-17df-4599-e053-1705fe0aef77
|
3
|
Behavioral test generation for the selection of BIST logic, file e0c31c09-e989-4599-e053-1705fe0aef77
|
2
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High-Level Synthesis of Parallel Specifications Coupling Static and Dynamic Controllers, file e0c31c11-89ce-4599-e053-1705fe0aef77
|
2
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High-Level Synthesis Developments in the Context of European Space Technology Research (Invited Talk), file 6e12387e-361f-42f4-83e9-744c80536731
|
1
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Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs, file e0c31c07-c1eb-4599-e053-1705fe0aef77
|
1
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Functional Test Generation, file e0c31c07-d803-4599-e053-1705fe0aef77
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1
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Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems, file e0c31c07-ea72-4599-e053-1705fe0aef77
|
1
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A design methodology to implement memory accesses in High-Level Synthesis, file e0c31c07-f1a4-4599-e053-1705fe0aef77
|
1
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The hArtes Tool Chain, file e0c31c07-f97c-4599-e053-1705fe0aef77
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1
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Totale |
19.969 |