Modern System-on-Chip (SoC) architectures are increasingly composed of Intellectual Property (IP) blocks, usually designed and provided by different vendors. This burdens system designers with complex system-level integration and verification. In this paper, we propose an approach that leverages HLS techniques to automatically find bugs in designs composed of multiple IP blocks. Our method is particularly suitable for industrial adoption because it works without exposing sensitive information (e.g., the design specification or the component generation process). This advocates the definition and the adoption of an interoperable format for cross-vendor hardware bug detection.

Enabling Automated Bug Detection for IP-based Designs using High-Level Synthesis

Pietro Fezzardi;Christian Pilato;Fabrizio Ferrandi
2018

Abstract

Modern System-on-Chip (SoC) architectures are increasingly composed of Intellectual Property (IP) blocks, usually designed and provided by different vendors. This burdens system designers with complex system-level integration and verification. In this paper, we propose an approach that leverages HLS techniques to automatically find bugs in designs composed of multiple IP blocks. Our method is particularly suitable for industrial adoption because it works without exposing sensitive information (e.g., the design specification or the component generation process). This advocates the definition and the adoption of an interoperable format for cross-vendor hardware bug detection.
Computer bugs;Hardware;Hardware design languages;IP networks;Intellectual property;Optimization;Software;Bug Detection;High-Level Synthesis;IP Protection;Intellectual Property
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1052325
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