The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip, while having to meet strict market demands which force to face always shortening design times. In general, the ideal design methodology shall support the exploration of the highest possible number of alternatives (in terms of HW-SW architectures) starting in the early design stages as this will prevent costly correction efforts in the deployment phase. The present paper will propose a new methodology for tackling the design exploration problem, with the aim of providing a solution in terms of optimal partitioning with respect of the overall system performance.

System-level metrics for hardware/software architectural mapping

FERRANDI, FABRIZIO;LANZI, PIER LUCA;SCIUTO, DONATELLA;TANELLI, MARA
2004-01-01

Abstract

The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip, while having to meet strict market demands which force to face always shortening design times. In general, the ideal design methodology shall support the exploration of the highest possible number of alternatives (in terms of HW-SW architectures) starting in the early design stages as this will prevent costly correction efforts in the deployment phase. The present paper will propose a new methodology for tackling the design exploration problem, with the aim of providing a solution in terms of optimal partitioning with respect of the overall system performance.
Electronic Design, Test and Applications, Proceedings. DELTA 2004. Second IEEE International Workshop on
computer architecture;embedded systems;software architecture;software metrics;software performance evaluation;systems analysis;HW-SW architectures;communication performance estimation;embedded systems design;hardware performance estimation;hardware/software architectural mapping;optimal partitioning;software performance estimation;system level metrics;Application software;Computer architecture;Delay estimation;Design methodology;Embedded system;Hardware;Modeling;Performance analysis;Software performance;System performance
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/262750
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