VLIW core processors are becoming more and more interesting for high-end embedded applications, in particular in the area of multimedia. Only few approaches have been proposed to test at-speed microprocessors. Moreover, the unique architectural peculiarities of VLIW processors have not yet been exploited. In this paper we propose a method aimed at the generation of functional tests made of valid instructions, and then applicable at speed, exploiting the features of pure VLIW architectures like the explicit instruction parallelism and the functional units visibility. The approach, starting from an HDL description of the functional unit under test, drives, by means of what we called projection over the instructions, an ATPG tool generating test patterns made of valid instructions. Visibility of operations results is then achieved through the exploitation of the explicit instruction level parallelism. Experiments on a VHDL model of VLIW show that the generated patterns are effective to test the processor at gate-level

An Approach to Functional Testing of VLIW Architectures

BRUSCHI, FRANCESCO;FERRANDI, FABRIZIO;SCIUTO, DONATELLA
2000

Abstract

VLIW core processors are becoming more and more interesting for high-end embedded applications, in particular in the area of multimedia. Only few approaches have been proposed to test at-speed microprocessors. Moreover, the unique architectural peculiarities of VLIW processors have not yet been exploited. In this paper we propose a method aimed at the generation of functional tests made of valid instructions, and then applicable at speed, exploiting the features of pure VLIW architectures like the explicit instruction parallelism and the functional units visibility. The approach, starting from an HDL description of the functional unit under test, drives, by means of what we called projection over the instructions, an ATPG tool generating test patterns made of valid instructions. Visibility of operations results is then achieved through the exploitation of the explicit instruction level parallelism. Experiments on a VHDL model of VLIW show that the generated patterns are effective to test the processor at gate-level
High-Level Design Validation and Test Workshop, 2000. Proceedings. IEEE International
9780769507866
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/247941
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